Manufact.
Intel
various
STM
PHILIPS
DALLAS/MAXIM
DALLAS/MAXIM
SILABS
AD
GOAL
GOAL
ATMEL
WINBOND
TI
Type
8051
RD2 (incl. P89C668)
uPSD3354
P89LPC935
DS80C320
DS89C450
C8051F120
ADuC841
VERSA1
VERSA MIX VMX1020
AT89LP4052
W77E516
MSC1211Y5
max.freq.
12MHz
20MHz
40MHz
12MHz
33MHz
33MHz
100MHz
20MHz
16MHz
14MHz
20MHz
40MHz
30MHz
SRAM
no
0.75kB (1kB-7.75kB)
32kB (program may execute)
0.5kB
no
1kB
8kB
2kB (can contain stack)
1kB
1kB
no
1kB
1kB (program can execute)
FLASH
4kB
64kB (+8kB)
256kB+32kB
8kB
no
64kB
128kB
62kB
64kB(+2kB OTP)
56kB
4kB
64kB+4kB
32kB (can be mapped data)
EEPROM
no
(2kB)
no
0.5kB
no
no
no
4kB
no
no
64B
no
bus
UART
UART, (I2C, SPI)
2xUART (IrDA), SPI, I2C
UART, I2C, SPI
2xUART
2xUART
2xUART,I2C,SPI
UART, I2C or SPI
2xUART, SPI, RS485
2xUART, SPI, I2C, RS485
UART, SPI
2xUART
2xUART, SPI, I2C
other
PCA, WDT
16 macrocell PLD, freely mappable FLASH/RAM via PLD, JTAG onchip debug, PCA, WDT, BOD, 8MUX 10bit 100ksps ADC, push-pull output (8x)
onchip RC oscillator, 2x 4MUX 8bit ADC, push-pull outputs, 2x comparator, BOD, WDT, RTC, capture/compare unit
BOD, WDT
BOD, WDT
onchip oscillator + PLL, onchip JTAG debugger, 8MUX 12bit 100ksps ADC, 8MUX 8bit 500ksps ADC, 2x 12bit DAC, MAC, 5x 16bit timers, WDT, BOD, onchip temperature sensor, PCA, push-pull outputs, partially exchangable
8MUX 420kSPS 12bit ADC, on chop reference, 2x12bit DAC, PWM, on chip temperature monitor, WD, power supply monitor
4MUX 12bit ADC
BOD, MAC
onchip debugger (UART), 3xcompare/capture, onchip voltage reference, 4x16-bit PWM, 4MUX 12bit 10kSps ADC, programmable current source, OPAMP, 2x digipot, 1x switch, BOD, WDT
WDT,BOD,PO R,Push-pull capable IO, comparator, PWM
WDT,WaitState for XRAM
8xMUX 24-bit ADC + PGA, 4x16-bit DAC, onchip reference, WaitState, BOD, WDT, LowVoltage detect, 16-bit PWM, 2 HW breakpoints, boot+debug ROM
package
DIL40, PLCC44
DIL40, PLCC44 (TQFP44)
TQPF52, TQFP80
TSSOP28, PLCC28, HVQFN28
DIP40, PLCC44, TQFP44
DIP40, PLCC44, TQFP44
TQFP100
PQFP52, CSP56
PQFP44
QFP64
DIL20,SOIC20, TSSOP20
DIL40,PLCC44, QFP44
TQFP64
supply volt.
5V
5V (3V)
5V+3.3V/3.3V
3.3V
5V
5V
3.3V
3V/5V
5V
5V
2.4-5V
5V
2.7-5V
flash programming
parallel
parallel, UART ISP, IAP
parallel, JTAG ISP, IAP
parallel, SPI-like "ICP", IAP (enabling UART ISP)
no
UART ISP, IAP
JTAG, IAP
parallel, UART ISP, IAP
I2C (12V)
I2C (12V)
parallel, SPI
parallel, IAP
parallel, UART
DPTR
1
2
2, autotoggle, autoinc/dec
2
2 (different SFR)
2 (different SFR), autotoggle, autoinc/dec
1
2, autotoggle, autoinc/dec/LSB- toggle
2 (different SFR)
2 (different SFR)
1
2
2 (different SFR)
external memory
yes
yes
yes (80-pin only)
no
yes
yes
data only (A-bus may be non-muxed)
data only (up to 16MB)
no
no
no
yes
yes
Mnemonic
Description
Size(bytes)
Hex Code
12x
6x
4x
2x
4x
1x
1x
1x
4x
1x
1x
4x
4x
Arithmetic instructions
ADD A, Rn
Add register to A
1
28-2Fh
1
1
1
1
1
1
1
1
1
1
1
1
1
ADD A, direct
Add direct byte to A
2
25h
1
1
1
1
2
2
2
2
2
2
2
2
2
ADD A, @Ri
Add data memory to A
1
26-27h
1
1
1
1
1
2
2
2
1
2
2
1
1
ADD A, #data
Add immediate to A
2
24h
1
1
1
1
2
2
2
2
2
2
2
2
2
ADDC A, Rn
Add register to A with carry
1
38-3Fh
1
1
1
1
1
2
1
1
1
1
1
1
1
ADDC A, direct
Add direct byte to A with carry
2
35h
1
1
1
1
2
2
2
2
2
2
2
2
2
ADDC A, @Ri
Add data memory to A with carry
1
36-37h
1
1
1
1
1
2
2
2
1
2
2
1
1
ADDC A, #data
Add immediate to A with carry
2
34h
1
1
1
1
2
2
2
2
2
2
2
2
2
SUBB A, Rn
Subtract register from A with borrow
1
98-9Fh
1
1
1
1
1
1
1
1
1
1
1
1
1
SUBB A, direct
Subtract direct byte from A with borrow
2
95h
1
1
1
1
2
2
2
2
2
2
2
2
2
SUBB A, @Ri
Subtract data memory from A with borrow
1
96-97h
1
1
1
1
1
2
2
2
1
2
2
1
1
SUBB A, #data
Subtract immediate from A with borrow
2
94h
1
1
1
1
2
2
2
2
2
2
2
2
2
INC A
Increment A
1
04h
1
1
1
1
1
1
1
1
1
1
1
1
1
INC Rn
Increment register
1
08-0Fh
1
1
1
1
1
1
1
1
1
2
1
1
1
INC direct
Increment direct byte
2
05h
1
1
1
1
2
2
2
2
2
3
2
2
2
INC @Ri
Increment data memory
1
06-07h
1
1
1
1
1
2
2
2
1
3
2
1
1
DEC A
Decrement A
1
14h
1
1
1
1
1
1
1
1
1
1
1
1
1
DEC Rn
Decrement register
1
18-1Fh
1
1
1
1
1
1
1
1
1
2
1
1
1
DEC direct
Decrement direct byte
2
15h
1
1
1
1
2
2
2
2
2
3
2
2
2
DEC @Ri
Decrement data memory
1
16-17h
1
1
1
1
1
2
2
2
1
3
2
1
1
INC DPTR
Increment data pointer
1
A3h
2
2
2
2
3
1
1
3
3
1
2
2
3
MUL AB
Multiply A by B
1
A4h
4
4
4
4
5
9
4
9
5
5
2
5
5
DIV AB
Divide A by B
1
84h
4
4
4
4
5
10
8
9
5
5
4
5
5
DA A
Decimal adjust A
1
D4h
1
1
1
1
1
2
1
2
1
1
1
1
1
Logical Instructions
ANL A, Rn
AND register to A
1
58-5Fh
1
1
1
1
1
1
1
1
1
1
1
1
1
ANL A, direct
AND direct byte to A
2
55h
1
1
1
1
2
2
2
2
2
2
2
2
2
ANL A, @Ri
AND data memory to A
1
56-57h
1
1
1
1
1
2
2
2
1
2
2
1
1
ANL A, #data
AND immediate to A
2
54h
1
1
1
1
2
2
2
2
2
2
2
2
2
ANL direct, A
AND A to direct byte
2
52h
1
1
1
1
2
2
2
2
2
3
2
2
2
ANL direct, #data
AND immediate data to direct byte
3
53h
2
2
2
2
3
3
3
3
3
4
3
3
3
ORL A, Rn
OR register to A
1
48-4Fh
1
1
1
1
1
1
1
1
1
1
1
1
1
ORL A, direct
OR direct byte to A
2
45h
1
1
1
1
2
2
2
2
2
2
2
2
2
ORL A, @Ri
OR data memory to A
1
46-47h
1
1
1
1
1
2
2
2
1
2
2
1
1
ORL A, #data
OR immediate to A
2
44h
1
1
1
1
2
2
2
2
2
2
2
2
2
ORL direct, A
OR A to direct byte
2
42h
1
1
1
1
2
2
2
2
2
3
2
2
2
ORL direct, #data
OR immediate data to direct byte
3
43h
2
2
2
2
3
3
3
3
3
4
3
3
3
XRL A, Rn
Exclusive-OR register to A
1
68-6Fh
1
1
1
1
1
1
1
1
1
1
1
1
1
XRL A, direct
Exclusive-OR direct byte to A
2
65h
1
1
1
1
2
2
2
2
2
2
2
2
2
XRL A, @Ri
Exclusive-OR data memory to A
1
66-67h
1
1
1
1
1
2
2
2
1
2
2
1
1
XRL A, #data
Exclusive-OR immediate to A
2
64h
1
1
1
1
2
2
2
2
2
2
2
2
2
XRL direct, A
Exclusive-OR A to direct byte
2
62h
1
1
1
1
2
2
2
2
2
3
2
2
2
XRL direct, #data
Exclusive-OR immediate to direct byte
3
63h
2
2
2
2
3
3
3
3
3
4
3
3
3
CLR A
Clear A
1
E4h
1
1
1
1
1
1
1
1
1
1
1
1
1
CPL A
Compliment A
1
F4h
1
1
1
1
1
1
1
1
1
1
1
1
1
RL A
Rotate A left
1
23h
1
1
1
1
1
1
1
1
1
1
1
1
1
RLC A
Rotate A left through carry
1
33h
1
1
1
1
1
1
1
1
1
1
1
1
1
RR A
Rotate A right
1
03h
1
1
1
1
1
1
1
1
1
1
1
1
1
RRC A
Rotate A right through carry
1
13h
1
1
1
1
1
1
1
1
1
1
1
1
1
SWAP A
Swap nibbles of A
1
C4h
1
1
1
1
1
1
1
1
1
1
1
1
1
Data Transfer Instructions
MOV A, Rn
Move register to A
1
E8-EFh
1
1
1
1
1
1
1
1
1
1
1
1
1
MOV A, direct
Move direct byte to A
2
E5h
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV A, @Ri
Move data memory to A
1
E6-E7h
1
1
1
1
1
2
2
2
1
2
2
1
1
MOV A, #data
Move immediate to A
2
74h
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV Rn, A
Move A to register
1
F8-FFh
1
1
1
1
1
1
1
1
1
2
1
1
1
MOV Rn, direct
Move direct byte to register
2
A8-AFh
2
2
2
2
2
2
2
2
2
4
2
2
2
MOV Rn, #data
Move immediate to register
2
78-7Fh
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV direct, A
Move A to direct byte
2
F5h
1
1
1
1
2
2
2
2
2
3
2
2
2
MOV direct, Rn
Move register to direct byte
2
88-8Fh
2
2
2
2
2
2
2
2
2
3
2
2
2
MOV direct, direct
Move direct byte to direct byte
3
85h
2
2
2
2
3
3
3
3
3
4
3
3
3
MOV direct, @Ri
Move data memory to direct byte
2
86-87h
2
2
2
2
2
2
2
2
2
4
2
2
2
MOV direct, #data
Move immediate to direct byte
3
75h
2
2
2
2
3
3
3
3
3
3
3
3
3
MOV @Ri. A
Move A to data memory
1
F6-F7h
1
1
1
1
1
1
2
2
1
3
1
1
1
MOV @Ri, direct
Move direct byte to data memory
2
A6-A7h
2
2
2
2
2
2
2
2
2
5
2
2
2
MOV @Ri, #data
Move immediate to data memory
2
76-77h
1
1
1
1
2
2
2
2
2
3
2
2
2
MOV DPTR, #data16
Move immediate to data pointer
3
90h
2
2
2
2
3
3
3
3
3
3
3
3
3
MOVC A, @A+DPTR
Move code byte relative DPTR to A
1
93h
2
2
2
2
3
3
3
4
3
3
3
2
3
MOVC A, @A+PC
Move code byte relative PC to A
1
83h
2
2
2
2
3
3
3
4
3
3
3
2
3
MOVX A, @Ri
Move external data (A8) to A
1
E2-E3h
2
2
2
2
2-9
2
3
4
3
3-10
-
2-9
2-9
MOVX A, @DPTR
Move external data (A 16) to A
1
E0h
2
2
2
2
2-9
2
3
4
3
3-10
-
2-9
2-9
MOVX @Ri, A
Move A to external data (A8)
1
F2-F3h
2
2
2
2
2-9
2
3
4
3
4-11
-
2-9
2-9
MOVX @DPTR, A
Move A to external data (A 16)
1
F0h
2
2
2
2
2-9
2
3
4
3
4-11
-
2-9
2-9
PUSH direct
Push direct byte onto stack
2
C0h
2
2
2
2
2
2
2
2
2
4
2
2
2
POP direct
Pop direct byte from stack
2
D0h
2
2
2
2
2
2
2
2
2
3
2
2
2
XCH A, Rn
Exchange A and register
1
C8-CFh
1
1
1
1
1
2
1
1
1
2
1
1
1
XCH A, direct
Exchange A and direct byte
2
C5h
1
1
1
1
2
3
2
2
2
3
2
2
2
XCH A, @Ri
Exchange A and data memory
1
C6-C7h
1
1
1
1
1
3
2
2
1
3
2
1
1
XCHD A, @Ri
Exchange A and data memory nibble
1
D6-D7h
1
1
1
1
1
3
2
2
1
3
2
1
1
Boolean Instructions
CLR C
Clear carry
1
C3h
1
1
1
1
1
1
1
1
1
1
1
1
1
CLR bit
Clear direct bit
2
C2h
1
1
1
1
2
2
2
2
2
3
2
2
2
SETB C
Set carry
1
D3h
1
1
1
1
1
1
1
1
1
1
1
1
1
SETB bit
Set direct bit
2
D2h
1
1
1
1
2
2
2
2
2
3
2
2
2
CPL C
Complement carry
1
B3h
1
1
1
1
1
1
1
1
1
1
1
1
1
CPL bit
Complement direct bit
2
B2h
1
1
1
1
2
2
2
2
2
3
2
2
2
ANL C, bit
AND direct bit to carry
2
82h
2
2
2
2
2
2
2
2
2
2
2
2
2
ANL C, /bit
AND direct bit inverse to carry
2
B0h
2
2
2
2
2
2
2
2
2
2
2
2
2
ORL C, bit
OR direct bit to carry
2
72h
2
2
2
2
2
2
2
2
2
2
2
2
2
ORL C, /bit
OR direct bit inverse to carry
2
A0h
2
2
2
2
2
2
2
2
2
2
2
2
2
MOV C, bit
Move direct bit to carry
2
A2h
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV bit, C
Move carry to direct bit
2
92h
2
2
2
2
2
2
2
2
2
3
2
2
2
Branching Instructions
ACALL addr 11
Absolute call to subroutine
2
11-F1h
2
2
2
2
3
2
3
3
3
6
3
3
3
LCALL addr 16
Long call to subroutine
3
12h
2
2
2
2
4
3
4
4
4
6
4
4
4
RET
Return from subroutine
1
22h
2
2
2
2
4
3
5
4
4
4
4
2
4
RETI
Return from interrupt
1
32h
2
2
2
2
4
3
5
4
4
4
4
2
4
AJMP addr 11
Absolute jump unconditional
2
01-E1h
2
2
2
2
3
2
3
3
3
3
3
3
3
LJMP addr 16
Long jump unconditional
3
02h
2
2
2
2
4
3
4
4
4
4
4
4
4
SJMP rel
Short jump (relative address)
2
80h
2
2
2
2
3
3
3
3
3
3
3
3
3
JC rel
Jump on carry = 1
2
40h
2
2
2
2
3
3
2/3
3
3
3
3
3
3
JNC rel
Jump on carry = 0
2
50h
2
2
2
2
3
3
2/3
3
3
3
3
3
3
JB bit, rel
Jump on direct bit = 1
3
20h
2
2
2
2
4
4
3/4
4
4
4
4
4
4
JNB bit, rel
Jump on direct bit = 0
3
30h
2
2
2
2
4
4
3/4
4
4
4
4
4
4
JBC bit, rel
Jump on direct bit = 1 and clear
3
10h
2
2
2
2
4
4
3/4
4
4
4
4
4
4
JMP @A+DPTR
Jump indirect relative DPTR
1
73h
2
2
2
2
3
3
3
3
3
2
3
2
3
JZ rel
Jump on accumulator = 0
2
60h
2
2
2
2
3
3
2/3
3
3
3
3
3
3
JNZ rel
Jump on accumulator 1= 0
2
70h
2
2
2
2
3
3
2/3
3
3
3
3
3
3
CJNE A, direct, rel
Compare A, direct JNE relative
3
B5h
2
2
2
2
4
5
3/4
4
4
4
4
4
4
CJNE A, #d, rel
Compare A, immediate JNE relative
3
B4h
2
2
2
2
4
4
3/4
4
4
4
4
4
4
CJNE Rn, #d, rel
Compare reg, immediate JNE relative
3
B8-BFh
2
2
2
2
4
4
3/4
4
4
4
4
4
4
CJNE @Ri, #d, rel
Compare ind, immediate JNE relative
3
B6-B7h
2
2
2
2
4
5
4/5
4
4
4
4
4
4
DJNZ Rn, rel
Decrement register, JNZ relative
2
D8-DFh
2
2
2
2
3
4
2/3
3
3
3
3
3
3
DJNZ direct, rel
Decrement direct byte, JNZ relative
3
D5h
2
2
2
2
4
5
3/4
4
4
4
4
4
4
Miscellaneous Instruction
NOP
No operation
1
00h
1
1
1
1
1
1
1
1
1
1
1
1
1
SerialISR:
PUSH PSW
2
2
2
2
2
2
2
2
2
4
2
2
2
PUSH ACC
2
2
2
2
2
2
2
2
2
4
2
2
2
SETB RS0
1
1
1
1
2
2
2
2
2
3
2
2
2
JBC TI,TI_ISR
2
2
2
2
4
4
4
4
4
4
4
4
4
TI_ISREnd:
JBC RI,RI_ISR
2
2
2
2
4
4
4
4
4
4
4
4
4
SerialISREnd:
POP ACC
2
2
2
2
2
2
2
2
2
3
2
2
2
POP PSW
2
2
2
2
2
2
2
2
2
3
2
2
2
RETI
2
2
2
2
3
3
5
4
4
4
4
2
3
TI_ISR:
MOV A,TI_PTR
1
1
1
1
2
2
2
2
2
2
2
2
2
JZ TI_ISREnd
2
2
2
2
3
3
2
3
3
3
3
3
3
DEC TI_PTR
1
1
1
1
2
2
2
2
2
3
2
2
2
ADD A,#LOW(TxBuff-1)
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV R0,A
1
1
1
1
1
1
1
1
1
2
1
1
1
MOV R2,P2
2
2
2
2
2
2
2
2
2
4
2
2
2
CLR A
1
1
1
1
1
1
1
1
1
1
1
1
1
ADDC A,#HIGH(TxBuff-1)
1
1
1
1
2
2
2
2
2
2
2
2
2
MOV P2,A
1
1
1
1
2
2
2
2
2
3
2
2
2
MOVX A,@R0
2
2
2
2
2
2
3
4
3
3
? (4)
2
2
MOV P2,R2
2
2
2
2
2
2
2
2
2
3
2
2
2
MOV SBUF,A
1
1
1
1
2
2
2
2
2
3
2
2
2
SJMP TI_ISREnd
2
2
2
2
3
3
3
3
3
3
3
3
3
RI_ISR:
MOV R1,RX_Head
2
2
2
2
2
2
2
2
2
4
2
2
2
MOV @R1,SBUF
2
2
2
2
2
2
2
2
2
5
2
2
2
INC R1
1
1
1
1
1
1
1
1
1
2
1
1
1
CJNE R1,#RXBuffEnd,RI_ISR_X1
2
2
2
2
4
4
4
4
4
4
4
4
4
MOV R1,#RXBuff
1
1
1
1
2
2
2
2
2
2
2
2
2
RI_ISR_X1:
MOV A,R1
1
1
1
1
1
1
1
1
1
1
1
1
1
CJNE A,RX_Tail,RI_ISR_X2
2
2
2
2
5
5
4
4
4
4
4
4
5
SJMP SerialISREnd
2
2
2
2
3
3
3
3
3
3
3
3
3
RI_ISR_X2:
MOV RX_Head,A
1
1
1
1
2
2
2
2
2
3
2
2
2
SJMP SerialISREnd
2
2
2
2
3
3
3
3
3
3
3
3
3
cycles
49
49
49
49
72
72
73
74
73
94
74
70
72
clocks
588
294
196
98
288
72
73
74
292
94
74
280
288
execution time [us]
49,00
14,70
4,90
8,17
8,73
2,18
0,73
3,70
18,25
6,71
3,70
7,00
9,60