11:19 13.10.2017 Throughout this document: I have no time nor energy to browse the errors found for older versions whenever a newer version appears. ST tends to correct some, but not all, then add more, or old errors surface later, or they consider some of them not to be an issue. And, of course, I am wrong at times, too. So, whoever would like to find out all of them, may want to start from an arbitrary older version. The page numbers don't match, but for each item there is usually enough accompanying text to be able to locate them. --- stm32f4xx.h v1.5.0 - missing mask definition for FLASH_CR_ERRIE - incorrectly named definition FLASH_SR_SOP, should read FLASH_SR_OPERR - FLASH_CR_SNB_4 is probably incorrectly defined as 0x40, as that would be the same as FLASH_CR_SNB_3 - all DBGMCU_APB2_FZ register symbols are incorrectly marked as DBGMCU_APB1_FZ (even the register name in the commenting header) - missing definitions for the ETH DMA descriptors - as they relate directly to the ETH hardware, they really belong here To ST: With ALL stm32fxxx.h - PLEASE include non-single-bit values definitions, PLUS both the mask AND the lowmost bit definition, PLEASE, thank you. I am willing to cooperate/help/discuss. Also, PLEASE, document all the changes/bugfixes in the accompanying Release notes, PLEASE, thank you. (Rationale: There are folks as me, who rely on the Release notes to find out relevant changes, as we don't replace the old version with newer blindly, and comparing them is a pain). --- STM32F405xx and STM32F407xx Datasheet DocID022152 Rev 8 September 2016 Tab9 Alternate function mapping - throughout the whole table, column AF12 is marked "FSMC/SDIO/OTG_FS". There is no OTG_FS function in AF12, but there are OTG_HS functions. This column should be thus labeled "FSMC/SDIO/OTG_HS". p128 and on - USB OTG FS characteristics - "This interface is present in both the USB OTG HS and USB OTG FS controllers." - both the title and this line is confusing. This chapter does not deal with particularities of the OTG_FS module, but deals with the characteristics of the FS_PHY, which is built together with both the OTG_FS and OTG_HS modules. Please use the word "PHY" to make this clear and on par with RM0090 rev.15 "34.3.2 Full-speed OTG PHY" and "35.3.3 Embedded Full-speed OTG PHY". p130 - in Table 61., no values are given for "PHY preparation time after the first transition of the input clock" --- STM32F40x and STM32F41x Errata sheet rev.6 (still there in rev.7) (and still there in rev.8) p8 - typo - VQSRT (instead of VSQRT) --- PM0214 rev 6 - STM32F3xxx and STM32F4xxx Cortex-M4 programming manual - bookmarks completely messed up p239 - both issues mentioned below for rev.5 remained PM0214 rev 5 - STM32F3xxx and STM32F4xxx Cortex-M4 programming manual p141 - in the description of instruction set, branch-and-control instructions should form a chapter of its own. It means, sub-chapter 3.9.4 should change to 3.10, 3.9.5-3.9.8 should be sub-chapters in 3.10; current 3.10 and 3.11 should change to 3.11 and 3.12. The same error is in the Cortex-M3 PM; the Cortex-M7 PM has got it right. p239 - in the chapter title, MMFSR is *status* register, not *address* register p239 - Bit 1 IACCVIOL - this is bit 0 in fact ---- PM0214 rev 4 - STM32F3xxx and STM32F4xxx Cortex-M4 programming manual p213 - the sentence starting "If you implement fewer than 8 priority bits..." is obviously a message from ARM to the vendor and should have not appeared in the public manual. Also, an explanation for PRIGROUP=0b000 is needed, as it's the reset state of this field. ---- PM0214 rev 3 - STM32F3xxx and STM32F4xxx Cortex-M4 programming manual p29 - in Table 13, the last two rows, Private Peripheral Bus and Memory mapped peripherals, have probably incorrect address ranges; instead of EDxxxxxx they should be E0xxxxxx p39 - the range given for vector table, "0x00000080 to 0x3FFFFF80", is in conflict with description of VTOR register on page 211, which indicates that the bottommost 9 bits are always zero p202 - the description of NVIC_STIR refers to USERSETMPEND bit, but it's in CCR not in SCR as the description says p206 - in Table 50, register SHCSR is incorrectly spelled as SHCRS - in the same table, register MMFAR is incorrectly spelled as MMAR p207 - description of bit DISDEFWBUF says, "[...] stores to memory is competed before next instruction.", should apparently be "completed" instead of "competed" p223 (and also twice on p220) - register MMFSR is errorneously labelled as "Memory Management Fault Address Register" (should be "... Status Register") - bit IACCVIOL is incorrectly labelled as Bit 1 (it is Bit 0) p227 - while the description of register CPUID on page 208 correctly states the reset value as 0x410FC241, the bits for this register in table 53 are incorrectly set to 0x411FC231 ---- UM1472 - STM32F4DISCOVERY User Manual, rev 2 p28 - table 5 indicates that pin PE2 is connected to CS_I2C/SPI of LIS302DL ( https://my.st.com/public/STe2ecommunities/mcu/Lists/STM32F4DISCOVERY/Flat.aspx?RootFolder=%2Fpublic%2FSTe2ecommunities%2Fmcu%2FLists%2FSTM32F4DISCOVERY%2FPE2%20or%20PE3&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580002E3D0FFCC5A9AA4A9C29C3EECB7CCDBF¤tviews=149 ) In reality (and according to schematics and supplied code), this pin is connected to PE3. ---- UM1879 - 32L476GDISCOVERY User Manual, rev.2 (I know it's not 'F4, but IMO it fits into this document too) p23 - in Table 7, SB17, SB15 (MFX USART RX,TX) for ON says "PA10 of STM32F103CBT6 are not connected to PB3 of STM32L476VGT6" which does not match the purpose of those solder bridges and is a result of copy-paste ---- AN2606 - Application Note: STM32 microcontroller system memory boot mode, rev 16 p65 (and p111) - in the "Connection to the peripheral" subsection, "or to the USART2_RX (PD6) and USART2_TX (PD5) pins" is mentioned, while the bootloader does not use USART2, rather, it uses USART3, on two pairs of pins. As this is apparently a copy/paste error, it repeats for both the STM32F40x/41x and the STM32F42x/43x variants. ---- AN4537 p3 - table 2, RAM size and other memories, for STM32F407xx/417xx, "128 Kbyte of SRAM including 64 Kbyte of CCM," should read "192 Kbyte of SRAM ..." ---- RM0090 rev 15 p150-151+p213-214 - all clickable links on "Figure 4" lead to "..\..\STR_IPs\MRCC\PIRANHA_rccu.pdf" (3+3 instances). These should lead to Figure 10 and Figure 9 respectively. p372 - in "OTG_FS WKUP" acronym, an underscore is missing - it would be nice to add to its description, that it's EXTI 18 (I know it's on p.383 but this table should contain it too) - there is no explanation in this or the OTG_FS chapter, how is this interrupt configured and triggered p379 - it would be nice to add to OTG_HS_WKUP description, that it's EXTI 20 (I know it's on p.383 but this table should contain it too) - there is no explanation in this or the OTG_HS chapter, how is OTG_HS_WKUP interrupt configured and triggered. The text on p.383 "EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event" is even more confusing; I could find no mention in the OTG_FS chapter for this configuration either. Is this again supposed to say "FS_PHY connected to the OTG_HS module"? There is no dedicated FS_PHY_in_OTG_HS text which would mention this interrupt, either. - there is no explanation in this or the OTG_HS chapter, how are OTG_HS_EP1_IN and OTG_HS_EP1_OUT interrupts configured and triggered. p415 - 1x typo "STM23" instead of "STM32", cf. rev.10 p413 p1160 - clickable link on "Section 4.3.4: Stop mode" leads to ..\..\STR_IPs\MRCC\PIRANHA_rccu.pdf -- cf. with what I've written below for rev.9 p1141 and rev.10 p1148... .both OTG chapters - textual search for "OTG_HS" finds one instance in the OTG_FS chapter; and for "OTG_FS" finds about half a dozen of them in the OTG_HS chapter p1260+p1295 - chapter "34.9 Dynamic update of the OTG_FS_HFIR register" explicitly allows changing OTG_FS_HFIR while the module is operating, while description of the only field in this register (FRIVL) contains " Do not change the value of this field after the initial configuration." - this is a contradiction p1273+p1326 - reset value of OTG_FS_GOTGCTL is given in the register's description as 0x00000800, in the table reset value of the reserved bits are not given but all other bits are given as 0 except CIDSTS which is given as 1, which assuming all reserved bits at 0 would yield 0x00010000; while in a rev.Z STM32F407 it is found to be 0x00100000. The same applies for OTG_HS_GOTGCTL. p1274+p1406 - the narrative for OTG_FS/HS_GOTGCTL.SRQ bit says "This discharge time varies between different PHYs and can be obtained from the PHY vendor.". Isn't ST the PHY vendor in this case? Please clarify. p1285+p1419 - OTG_FS_GINTMSK/OTG_HS_GINTMSK contain EPMISM bit as bit 17, according to description to enable "Endpoint mismatch interrupt"; there is no such interrupt described elsewhere and the respective bit 17 in OTG_FS_GINTSTS/OTG_HS_GINTSTS is marked as reserved. (There is a mention of endpoint mismatch around OTG_HS_GINTSTS.DATAFSUSP description; but I suspect this part of that narrative should not be there for the given configuration of this IP). p1291 - reset value of OTG_FS_GCCFG is given as 0x00000000, while in a rev.Z STM32F407 it is found to be 0x0000FFFF (btw. in the table at end of chapter, reset value of the reserved bits is not given at all; OTG_HS_GCCFG *is* 0x00000000 after reset as documented) p1292+p1327 - reset value of OTG_FS_CID is given at both those pages as 0x00001100, while in a rev.Z STM32F407 it is found to be 0x00001200 (btw. OTG_HS_CID *is* 0x00001100 after reset as documented) Also, the description says "This is a read only register containing the Product ID.", while the bits are marked as "rw" and experiment shows this is indeed a writable register. p1307 - OTG_FS_DIEPMSK.INEPNMM ought to mask "IN token received with EP mismatch" interrupt, but the respective bit5 in OTG_FS_DIEPINTx is marked as reserved (cf. also above OTG_FS_GINTMSK.EPMISM). While in OTG_HS_DIEPINTx this bit is present, I suspect it still should not be there for the given configuration of this IP. p1308+p1320 - the respective bit6 to mask OTG_FS_DOEPINTx.B2BSTUP is in OTG_FS_DOEPMSK marked as reserved (in HS, both the B2BSTUP mask and interrupt bits are present) p1394 - figure "SOF trigger output to TIM2 ITR1 connection" is unnumbered. There is also a clickable link to this figure on the same page, "Figure" with no number. p1336+p1486 - in "Device initialization" chapter in both OTG_FS and OTG_HS "programming model" description, item 3. says "... and supply the 5 volts across the pull-up resistor on the DP line". As the pullup is built-in into PHY, this should not be needed and is confusing, please remove. p1398+p1403+p1451-1453 - functionality of OTG_HS_DEACHHINT/OTG_HS_DEACHHINTMSK/OTG_HS_DIEPEACHMSK1/OTG_HS_DOEPEACHMSK1 is not explained. They are mentioned also in Fig. 412, but with no clear indication what endp_multi_proc_intrpt and endp_interrupt[31:0] signals are supposed to trigger. ---- RM0090 rev 13 p250 x 7.3.15 RCC APB2 peripheral clock enable register(RCC_APB2ENR), should be removed entirely - while ch.7 is for the '40x/41x, this subchapter contains RCC_APB2ENR for the '42x/'43x. Note, that there *is* ch. 7.3.14 containing the proper RCC_APB2ENR register for STM32F405/415/407/417. An assortment of OTG-related typos described in https://community.st.com/thread/31122 ---- RM0090 rev 12 An aesthetical/typographical one: the orientation of odd/even pages are swapped since page 2, restored on page 1740 and swapped again on the very last page 1744. If printed as a book, this would cause the vast majority of pages to have the page number in the inside. Throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 207 on page 1404, where *both* styles are used on the same constant, such as "0xX000h". p148 - in description of SBF flag, there's a link to CSBF bit, but this link leads to the chapter for 'F40x/F41x, even if this description is for 'F42x/'F43x. Note, that on p143, in description of the same flag for 'F40x/F41x, there's no such link. p633 and p677 - in TIMx_SR.UIF description, "refer to the synchro control register description" - there is no "synchro control register", this should be "slave mode control register (TIMx_SMCR)". Note, that this description is correct in TIM1/TIM8's chapter. p709 - below Table 106, the link to Memory map section is to "..\..\STM32F1_Piranha\RM0008\RM008_Body.pdf" (most links to that chapter have been removed between rev.9 and rev.10, including this one, which reappeared in rev 12 probably as a result of copy/paste from other manual. Three or four more links to this very chapter/table somehow survived, funnily they all are different in wording (which might have been the reason for their survival, probably having escaped a string search... :-) ) ) p1541 - in FSMC chapter, the following is written: "A Write FIFO, 2-word long (16-word long for STM32F42x and STM32F43x)" - but FSMC is *not* present in STM32F42x and STM32F43x... ---- RM0090 rev 11 p148 - in description of SBF flag, there's a link to CSBF bit, but this link leads to the chapter for 'F40x/F41x, even if this description is for 'F42x/'F43x. Note, that on p143, in description of the same flag for 'F40x/F41x, there's no such link. p625 and p667 - in TIMx_SR.UIF description, "refer to the synchro control register description" - there is no "synchro control register", this should be "slave mode control register (TIMx_SMCR)". Note, that this description is correct in TIM1/TIM8's chapter. p1530 - in FSMC chapter, the following is written: "A Write FIFO, 2-word long (16-word long for STM32F42x and STM32F43x)" - but FSMC is *not* present in STM32F42x and STM32F43x... ---- RM0090 rev 10 throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 206 on page 1392, where *both* styles are used on the same constant, such as "0xX000h". p68 - the wording of last paragraph of ch.2.3.1 hints, that the whole block of SRAM1+SRAM2(+SRAM3) could be remapped and accessed through I-/D-bus. According to description of SYSCFG_MEMRMP and also Table 3 and Table 4, and also the bulleted list in both "Physical remap in ..." subchapters, this is not true, and only SRAM1 could be remapped. p75 - as a footnote to Table 5, I suggest adding text which would clarify, that for the models which don't have the full 1Mbyte of FLASH, only the first FLASH sections up to the nominal FLASH capacity are valid p129 - (clickable) links to RCC_AHBxENR for STM32F42x/43x lead to incorrect chapter (chapter 7 instead of chapter 6). The sentence also misses links to respective RCC_APBxENR registers, which are also important for power saving through clock disabling. I suggest omitting all those links and replace the whole sentence by a sentence similar to the subsequent sentence, generally referring to RCC_AHBxENR and RCC_APBxENR, without particular links. p133 and p136 - Table 27 (related to STM32F405/07/15/17) should not contain links to the STM32F42/43-related Table62 (twice). Conversely, Table 29 should not contain links to Table 61. p137 - in Table 30, PWR_SR should be PWR_CSR p272 - typo - GPIOx_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) (the other one has been corrected... see this item for rev.9) p340 - the "this section applies to..." text under the heading of DMA2D chapter is missing, although this module is specific only to some of the devices p415 - 1x typo "STM23" instead of "STM32" (5x has been corrected since rev.9...) p415 - while from the equation for calculating temperature it can be inferred that the voltage-to-temperature curve has a negative slope (expressed as Avg_Slope), the text fails to say this clearly, which together with the fact that Avg_Slope in the datasheet is given as positive value, may come as surprise. I would suggest to add text clarifying this fact both into RM0090, and into the relevant datasheets below the table where value of Avg_Slope is given. p624 - description of UIF flag contains double-quotes instead of bullets/dashes; they are also misplaced (the first one needs to be omitted and one needs to be added to the last sentence). Ironically, this is bug is present only in the TIM2-TIM5 chapter; other chapters have the proper bullets/dashes, the TIM1/TIM8 chapter also contains a proper link. This again is an opportunity to point out that it would be better to rewrite the whole timer chapter, unifying all timers into one chapter with adding a clear description of the distinctions of the individual variants (I know the timer appnote and I still insist that this info does belong to the UM). p1148 - in item 10., there should be a *second* link to Section 5.3.4: Stop mode (STM32F405xx/07xx and STM32F415xx/17xx). In rev.9 there was *one* (broken) link to 5.3.4 and I commented that there should be a *second* link to 5.3.5; now there *one* link to 5.3.5 only. p1242 - in Fig.389, an empty "PA9" is left unconnected in the box depicting the MCU. While the text above the figure explains it (The VBUS pin can be freed by disabling the VBUS sensing option.) and similarly the text in subsequent 34.6.2, it might be worth adding it as a numbered note also to the picture, or at least a note saying something like "VBUS (PA9) may be left unconnected, see explanation in text". But then, the very same can be said also in case of USB peripheral, so Fig.388 should be updated accordingly, too. ---- RM0090 rev 9 [as far as I noticed, many if not most of these were taken into account in rev.10 - those I've checked to be fixed are marked x] Under heading of most of the chapters: - the canned text "This section applies to the whole STM32F4xx family, unless otherwise specified." could be made more specific for quite some of the modules (e.g. ETH is absent in the 'F4x5 devices). - this text is sometimes in italic without any good reason - funnily enough, the text has variations, e.g. the comma is missing in the canned text for the (TIM9 to TIM14) chapter, "device" is added for some other chapters throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 206 on page 1387, where *both* styles are used on the same constant, such as "0xX000h". Interestingly, compared to v5 of manual, the other constant I mentioned below for this particular table (0xXFFC) has been already fixed... :-) p62 x typo " Instructions may also be fetch" instead of "... fetched" p68 - the wording of last paragraph of ch.2.3.1 hints, that the whole block of SRAM1+SRAM2(+SRAM3) could be remapped and accessed through I-/D-bus. According to description of SYSCFG_MEMRMP and also Table 3 and Table 4, and also the bulleted list in both "Physical remap in ..." subchapters, this is not true, and only SRAM1 could be remapped. p75 - as a footnote to Table 5, I suggest adding text which would clarify, that for the models which don't have the full 1Mbyte of FLASH, only the first FLASH sections up to the nominal FLASH capacity are valid p105 x in description of FLASH_CR for STM32F42xxx/43xxx, in the table, font for "EERIE" is incorrectly big p107 x in description of FLASH_OPTCR for STM32F40x/41x, for Bits 27:16, the bold text reads incorrectly "nWRP[7:6]". While the correct description would be nWRP[11:0], sadly the style in description of these bitfields is inconsistent throughout the manual: in certain chapters the [x:y] ranges are omitted at all. p119 x clickable links "Section 6.2.8: RTC/AWU clock" and "Section 6.3.17: RCC Backup domain control register (RCC_BDCR)" lead to an external document ("....\STR_IPs\MRCC\Tiny_MANTA_RCC.pdf"). x clickable link "RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)" is duplicated, and its first copy leads to an external document ("....\STR_IPs\MRCC\Tiny_MANTA_RCC.pdf"). p129 x clickable links "RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)" and "RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)" for STM32F405/07/15/17 lead to an external document ("....\STR_IPs\MRCC\Tiny_MANTA_RCC.pdf"). p131 x clickable links "Section 6.3.17: RCC Backup domain control register (RCC_BDCR)" (twice on this page) and "Section 6.3.18: RCC clock control & status register (RCC_CSR)" lead to an external document ("....\STR_IPs\MRCC\Tiny_MANTA_RCC.pdf"). p133 and p136 - Table 27 (related to STM32F405/07/15/17) should not contain links to the STM32F42/43-related Table62 (twice). Conversely, Table 29 should not contain links to Table 61. p138 x clickable link "Section 6.3.17: RCC Backup domain control register (RCC_BDCR)" leads to an external document ("....\STR_IPs\MRCC\Tiny_MANTA_RCC.pdf"). p150 and p212 x clickable link "Figure 4" leads to an external document ("....\STR_IPs\MRCC\PIRANHA_rrcu.pdf"). p158 and p221 x in description of "Internal/external clock measurement using TIM5/TIM11", reference to Figure 18 (Figure 23) is made twice (presumably the second should have pointed to Figure 19 (Figure 24)) p226 x (and quite a couple of others, wherever PLL multiplicator is mentioned) - the text for PLLN field suggests, that 192<=PLLN<=432 is a fixed range, whereas this relationship is valid only for one particular input frequency, namely 1MHz. It should be stressed, that the allowed range follows from the chosen input frequency and the limits for output frequencies (perhaps except 0 and 1, but those would be invalid given the limited range of input and output frequencies anyway) p272 x typo - GPIOx_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) -- cf. same typo on p287 p287 x typo - GPIOx_OSPEEDER and GPIOB_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) (the same typo is in the description of bits/bitfields of the GPIO_OSPEEDR register in stm32f4xx.h; but that is probably not worth to fix to avoid compatibility problems) p328 x CHSEL[3:0] instead of CHSEL[2:0] in the bit description table p392, 413, 414 - 6x typo "STM23" instead of "STM32" p414 - while from the equation for calculating temperature it can be inferred that the voltage-to-temperature curve has a negative slope (expressed as Avg_Slope), the text fails to say this clearly, which together with the fact that Avg_Slope in the datasheet is given as positive value, may come as surprise. I would suggest to add text clarifying this fact both into RM0090, and into the relevant datasheets below the table where value of Avg_Slope is given. p415 x the note in 13.11 "Battery charge monitoring" is relevant only for STM32F42xxx/43xxx, the note should state that clearly p798 x in "PREDIV_A = Ox7F" capital letter "O" is used instead of digit "0". A stylistical remark: in "If COSEL is set and "PREDIV_S+1" is a...", instead of double-quotes, brackets should be used. p1141 - clickable link "Section 5.3.4: Stop mode" leads to an external document (....\STR_IPs\MRCC\PIRANHA_rrcu.pdf"). There should also be a second link to "5.3.5 Stop mode (STM32F42xxx and STM32F43xxx)". p1235 - in Fig.389, an artifact "P 9" is left in the box depicting the MCU. p1235 x a spurious closing bracket is after "A-device session request protocol" ---- RM0090 rev 8 p391, 412, 413 - 6x typo "STM23" instead of "STM32" p798 - in "PREDIV_A = Ox7F" capital letter "O" is used instead of digit "0". A stylistical remark: in "If COSEL is set and "PREDIV_S+1" is a...", instead of double-quotes, brackets should be used. p1106 - first line under ETH chapter title says, "This section applies to the whole STM32F4xx family..." but it's not present in STM32F4x5 devices p1236 - in Fig.389, an artifact "P 9" is left in the box depicting the MCU. p1236 - a spurious closing bracket is after "A-device session request protocol" ---- RM0090 rev 7 throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 205 on page 1385, where *both* styles are used on the same constant, such as "0xX000h". Interestingly, compared to v5 of manual, the other constant I mentioned below for this particular table (0xXFFC) has been already fixed... :-) p62 - typo " Instructions may also be fetch" instead of "... fetched" p65 - the 5 memory ranges for ETHERNET MAC in Tab.1 is confusing (the same is as Tab.10 in the STM32F405/407 datasheet v4, presumably other related datasheets as well) p68 - the wording of last paragraph of ch.2.3.1 hints, that the whole block of SRAM1+SRAM2(+SRAM3) could be remapped and accessed through I-/D-bus. According to description of SYSCFG_MEMRMP and also Table 3 and Table 4, and also the bulleted list in both "Physical remap in ..." subchapters, this is not true, and only SRAM1 could be remapped. p197 - although the reset source bits (bits 25-31) of RCC_CSR are marked as "rw", based on experimentation it appears they are in fact read-only. p198 - the RMVF bit appears to be auto-cleared, the bit's description fails to mention this. An aesthetical problem: "IWDGRSTF" is not set in bold as the names of other bits are. p269 - typo - GPIOx_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) -- cf. same typo on p284 p284 - typo - GPIOx_OSPEEDER and GPIOB_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) (the same typo is in the description of bits/bitfields of the GPIO_OSPEEDR register in stm32f4xx.h; but that is probably not worth to fix to avoid compatibility problems) p305 - aesthetical: in table 43, Stream7 column, both "USART1_TX" and "USART6_TX" are split to two lines (this was not the case in previous revisions of the manual) p325 - CHSEL[3:0] instead of CHSEL[2:0] in the bit description table p1060 - the text under "Dual CAN" heading is duplicated (except for the slightly different description of the referred figure) p1145 - the text "The PPS output is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR)." is probably not true, see https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/PTP%20PPS%20output%20on%20stm32f407¤tviews=41 p1175 - duplicates p1174 p1234 - in Fig.389, an artifact "P 9" is left in the box depicting the MCU. Also, this box contains both "STM32F2xx" and "STM32F4xx", presumably only the latter should be there (this is also in Fig.387 on p1228). ---- RM0090 rev 6 throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 205 on page 1384, where *both* styles are used on the same constant, as "0xX000h". Interestingly, compared to previous version of manual, the other constant I mentioned below for this particular table (0xXFFC) has been already fixed... :-) p62 - typo " Instructions may also be fetch" instead of "... fetched" p68 - the wording of last paragraph of ch.2.3.1 hints, that the whole block of SRAM1+SRAM2(+SRAM3) could be remapped and accessed through I-/D-bus. According to description of SYSCFG_MEMRMP and also Table 3 and Table 4, and also the bulleted list in both "Physical remap in ..." subchapters, this is not true, and only SRAM1 could be remapped. p269 - typo - GPIOx_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) -- cf. same typo on p284 p284 - typo - GPIOx_OSPEEDER and GPIOB_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) (the same typo is in the description of bits/bitfields of the GPIO_OSPEEDR register in stm32f4xx.h; but that is probably not worth to fix to avoid compatibility problems) p569 - in the description of bits CCR2 of TIMx_CCR2 register, a reference is given to bit OC2PE in TIMx_CCMR2 register. In fact, this bit is in TIMx_CCMR1 register. Similarly, in the description of bits CCR3/CCR4 of TIMx_CCR3/TIMx_CCR4 registers, reference is given to bits OC3PE/OC4PE in TIMx_CCMR3/TIMx_CCMR4 registers. There are no such registers, and both OC3PE and OC4PE bits are located in TIMx_CCMR2 register. This error repeats in the other timer chapters, where applicable. p783 - in 26.3.4, in description for WUCKSEL[2:1] = 11, in sentence starting "In this case 216 [...]" the "16" is probably supposed to be a superscript The following sentence, starting "When the initialization sequence...", does not belong to the description for WUCKSEL[2:1] = 11 and is supposed to start a separate paragraph. p816 - in Table 120, for RTC_CR, the last three bits are labelled as "WCKSEL", this should be "WUCKSEL" p1577 - chapter 36.6.9 should be numbered 36.7, as the table is common to both controllers within FSMC - compare how the respective chapter for FMC is numbered. Also, for consistency with other peripherals' registers table, the FMC_BCRx/FMC_BTRx registers should be ordered by their addresses (see similar remark for FMC). p1657 - incorrect addresses of FMC_BWTRx registers. Also, for consistency with other peripherals' registers table, the FMC_BCRx/FMC_BTRx registers should be ordered by their addresses (see similar remark for FSMC). ---- RM0090 rev 5 throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 206 on page 1380, where *both* styles are used on the same constant, as "0xX000h–0xXFFCh". p62 - typo " Instructions may also be fetch" instead of "... fetched" p68 - the wording of last paragraph of ch.2.3.1 hints, that the whole block of SRAM1+SRAM2(+SRAM3) could be remapped and accessed through I-/D-bus. According to description of SYSCFG_MEMRMP and also Table 4 and Table 5, this is not true, and only SRAM1 could be remapped. p269 - typo - GPIOx_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) -- cf. same typo on p284 p284 - typo - GPIOx_OSPEEDER and GPIOB_OSPEEDER (extra 'E', should be GPIOx_OSPEEDR) (the same typo is in the description of bits/bitfields of the GPIO_OSPEEDR register in stm32f4xx.h; but that is probably not worth to fix to avoid compatibility problems) p782 - in 26.3.4, in description for WUCKSEL[2:1] = 11, in sentence starting "In this case 216 [...]" the "16" is probably supposed to be a superscript The following sentence, starting "When the initialization sequence...", does not belong to the description for WUCKSEL[2:1] = 11 and is supposed to start a separate paragraph. p969 - in the text in Note under Table 144, the number in reference to (presumably) Table 144 is missing p989 - description of DR register, in the TDR description paragraph, refers to "Figure 1", which should probably point to the first figure of the USART section (i.e. Figure 296). ---- RM0090 rev 4 throughout the whole manual - Specific reference to 'F405/'F407/'F415/'F417 and general to 'F42xx/'F43xx should be the the other way round, in light of announcement of 'F429/'F439, which are substantially different from 'F427/'F437 and will apparently have a separate user manual throughout the whole manual - there are several places where hexadecimal constants are suffixed by 'h'; this is inconsistent with the C-style (0x prefix) in the rest of the manual - search for "00h" and "FFh" will reveal some of these places, but others have to be found "manually". One of the most ridiculous examples of this stylistic shortcoming is in Table 174 on page 1050, where *both* styles are used on the same constant, as "0xX000h–0xXFFCh". p 49 and on in chapter 2 - while on several places the two (three) SRAMs accessible through the bus matrix are referred to as SRAM1, SRAM2, (SRAM3), on other places this has been replaced by a vague and confusing "112, 64, and 16 Kbytesinternal SRAMs". I'd recommend to stick to SRAM1..SRAM3. p49 - "Seven slaves", and then 8 are listed (7 are for 'F40x/'F41x; 8 are for 'F427/'F437) p50/p51 - should the master ports on Fig1/Fig2 and subsequent subchapter titles be labelled as S0..S7, and the slave ports as M0..M7? p51 - typo " Instructions may also be fetch" instead of "... fetched" p53 - clickable link for SYSCFG section leads to an external document (....\STR_IPs\SYSCFG\Mangusta_SYSCFG.pdf) p55 - in ch.2.3.1, sentence starting "AHB masters support concurrent SRAM accesses..." should probably be as a separate paragraph, outside the "bulleted" list. Also, the bulleted list now lists four blocks of SRAM while the text above it refers to three (a block has been added for the new 'F42x/F43x). A table would be more appropriate perhaps. Also, the 64kB SRAM is elsewhere referred to as CCM SRAM, why not here. The other two (three) blocks of SRAM could be referred to as SRAM1 to SRAM3, too. I'd rephrase the whole section, making clear that there are two (three) blocks of SRAM accessible through the bus matrix, and one which is not. Also, in the last section, it should be made clear that it's only SRAM1 which could be accessed through all thre buses of the core and which could be remapped to the boot area. Also, it may not be as advantageous to remap as the last sentence in this section suggests, see 2012_STM32 Technical Updates - Issue 1.pdf page 45 p62 - In table 7, the maximum clock frequency for 0 waitstate for the lower two voltage ranges are now in discrepancy with corresponding values in the datasheet (datasheet rev.3, table 14). While the footnote stating operation allowed between 1.7V and 1.8V at a restricted temperature range has been removed since previous version, the datasheet ('F405/'F407) has not been updated, shouldn't they be in sync in this regard? As this table is apparently process-dependent, it should perhaps be moved to datasheet and merged with said table 14 therein. p69 and 70 - tables 11 and 12 it is funny that visual appearance of these two - otherwise indentical (except the one extra option byte for 'F427/'F437) tables - is different. With no loss to legibility and little work, these two tables could be merged to one, cutting down the unnecessary fluff. p111 - typo in the chapter title "Reset and clock control for" (the "for" was not there in rev.1 of the manual) p116 - Fig.14, as well as the text under "External source (HSE bypass)" (and also the text under "External source (LSE bypass)" on page 118) indicates that upon bypass the OSC_OUT/OSC32_OUT pin "should be left Hi-Z" (spelled inconsistently as "HiZ" in the picture, and as "hi-Z" in the text under "External source (HSE bypass)"). This presumably means, that there should be no external circuitry connected to this pin. However, the figure may be (incorrectly?) interpreted also as "the internal circuitry leaves this pin Hi-Z when bypass is set". If this is not the case and the internal circuitry drives these pins even in bypass mode, perhaps a different wording ("should be left unconnected") should be used; as "Hi-Z" usually refers to the state when a pin is not driven by an internal circuitry. p118 - typo "The LSE crystal is a 32.768 kHz low-speed external (LSE) crystal or ceramic resonator." Should probably read "The LSE clock is generated using a 32.768kHz low speed external crystal or ceramic resonator." The same error is repeated in the beginning of the next section, "The LSE crystal is switched on and off...", should probably read "The LSE clock (or oscillator) is switched on and off..." p175 - Clickable link for "Power control register (PWR_CR)" and "Section 5.1.2 on page 67" lead to an external document (....\STR_IPs\MRCC\PIRANHA_rrcu.pdf"). Referring to "Section 5.1.2 on page 67" for backup domain access is incorrect by page number (backup domain access procedure and usage of DBP bit is described on page 91). p175 - Description of LSEBYP bit says "set and cleared by software to bypass oscillator in debug mode". However, the description of LSE bypass mode on page 118 does not indicate that the bypass mode would require "debug mode". p186 - "Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes." This is confusing. How else could be these registers accessed? p187 - Table 27 for MODER(i)[1:0]=10 (alternate function), the IO configuration column can be interpreted so, that when set to AF, the pin is always output. While there is a remark in 7.3.11 saying "the output buffer is driven by the signal coming from the peripheral (*transmitter enable* and data), which explains, that the peripheral controls whether the pin in AF mode functions as input or output, this should be made clear both in said table, and also in drawings in Figure 17 and Figure 22. p188/189 and elsewhere - in several places, CortexTM-M4F EVENTOUT is referred to; there is no explanation of this feature in ST's nor ARM's publicly available documents. This is unnecessary and confusing. Either a concise explanation should be provided, or else this feature (thus AF15) should be marked as reserved. p199 and on - there is a superfluous slash in (x = A..I/) at several places (also in the form of "C..I/" in the table at the end of chapter). Funnily, some of them have been corrected between rev.3 and rev.4. A "search" facility available in common pdf readers easily reveals all of them. p199 - in description of GPIOx_OTYPER register, the individual bits are marked as OTy[1:0], which is incorrect, as there is only one bit per pin in this register p199 - in description of GPIOx_OSPEEDR register, a mention of the recommended use of compensation cell for speeds 50MHz and 100MHz, together with link to the related chapter 8.1, should be added Also, the description for highest speed ("11: 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF)") appers to be a mistake (higher speed is expected for lower capacitive load); unfortunately the current version 3 of datasheet provides confusingly non-matching data. p200 - in description of GPIOx_IDR and GPIOx_ODR registers, the individual bits are marked as IDRy[15:0] and ODRy[15:0], which is incorrect, as there is only one bit per pin in this register p206 - in description of SYSCFG_MEMRMP register's reset value after "Reset value:", a closing bracket is missing. Also, the description of the MEM_MODE field should contain a reference to chapter 2.4. Also, the expression "SRAM1" could be used to refer to the 112kB SRAM, consistently with chapter 2. p207 - in description of MII_RMII_SEL bit of SYSCFG_PMC, in the text "RMII Why interface is selected" the word "Why" is probably some spurious relict. The same in the copy of SYSCFG_PMC register description for STM32F427/F437. p208 - in description of SYSCFG_EXTICR1 register, there is an incorrect index in "0101: PF[C] pin". Also, the reset value is given only as a 16-bit value, which is confusingly different from other registers' description. Also, with little effort, descriptions of all four SYSCFG_EXTICRy (y=1..4) registers could be merged, reducing the unnecessary bloat. p244 - typo in description of FTH[1:0] in DMA_SxFCR: "... when the DMIS value is zero." should read "... when the DMDIS value is zero." p249 - SysTick calibration value according to PM0214: STM32F4xxx Cortex-M4 programming manual, in chapter 4.5.4, should provide 1ms period if HCLK is at maximum, whereas the provided value 18750 is related to a lower than maximum HCLK frequency (150MHz rather than 168MHz). Moreover, while this value is supposed to result in 1ms SysTick interrupt when used as reload value with HCLK=150MHz (and SysTick clocked from HCLK/8) - however, real reload value should be one less than that, so this value in fact results in 1ms reload for HCLK=150.008MHz ... p262 - the description of bits in register EXTI_SWIER says, "Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR." According to both Fig.26 and experiments, this is not entirely true - the corresponding bit in interrupt mask register needs to be set at the moment of write, otherwise the bit in pending register won't be set. Accordingly, the following sentence needs rephrasing, too. Also, while it's true that this register's bit can be cleared by writing 1 into the pending register as the last sentence says, it might be worth noting that it can be cleared by the ordinary writing 0 into it, too. p262 - the desription of bits in register EXTI_PR says, "This bit is cleared by writing a 1 to the bit or by changing the sensitivity of the edge detector." According to experiments, the latter is not true - changing value of corresponding bit in either of the EXTI_RTSR or EXTI_FTSR register did not clear the EXTI_PR bit. p273 - there is insufficient description of what constitutes an external trigger for ADC from TIMx_CHy. The vague description at the beginning of the subchapter appears to indicate that this is equivalent to the compare event (i.e. match between the respective CC register and counter, as defined in Timer chapters) for the given timer CC channel; from experimentation follows that this is not true at all. It appears, that the ADC trigger is tied to the *output* of the compare circuitry just before it enters the GPIO MUX; from which it is clear, that the timer channel must be configured for compare output, its mode configured so that it actually outputs a waveform (e.g. OCxM cannot be set to FROZEN, CCxE has to be set, etc.), even if it does need to go to actual output pin through the GPIO MUX. A clear description of this issue is needed. Also, it might be a good idea to add a link to this chapter from ther respective Timer chapter (hard to say which one, given the mess the Timer chapters are). p276 - a reference is made to a nonexistent DMA_SxRTR register ("number of transfers configured in the DMA controller’s DMA_SxRTR register"). Probably, the DMA_SxNDTR register is meant by this. Interestingly, in the same subchapter 11.8.1, reference is made to the same register as "adjust destination address and NDTR counter"; again, it would be more appropriate to use the full name of that register (DMA_SxNDTR). p330 - text in chapter 13.4 DCMI Clocks says "The maximum PIXCLK period must be higher than 2.5 HCLK periods." Clearly, the *minimum* PIXCLK period must be higher than 2.5 HCLK periods; in other words, the maximum PIXCLK *frequency* must be less than 0.4 times fHCLK (this is what the datasheet says too, btw.). p391 and p392 - on Figures 116 and 117 (also Fig.186 and Fig.187 on p500), signals such as "cnt_en" are in small letters, whereas everywhere else they are in capital letters p396 - description of MMS bits says "MMS[1:0]" although MMS has 3 bits (the same description for other groups of timers, e.g. on p461 and p503, and p532, simply omits the [x:y] bit size descriptor, as if it would be a single-bit value) p483 - chapter 16.3 apparently ought to be a subchapter in chapter 16.2 (and numbering of other chapters moved accordingly) p483 and p503 and wherever else applicable - according to diagram on Fig.165 and also Tab.79, there is no TRGO output from TIM9 and TIM12, yet chapter 16.5.2 deals with the related MMS bits in TIMx_CR2. p483 and wherever else applicable - conversely to the previous, TIM10, TIM11, TIM13 and TIM14 apparently DO have TRGO output, as according to Tab.79 they serve as masters (for TIM9 and TIM12). However, there is no TIMx_CR2 in the 16.6 subchapter, nor in table 83; and even the reference to it in Figure 166 has been removed (as compared to Rev.1). p516 - some relic "10/11/13/14" just above header of chapter 16.6.2 p632 - chapter 23.3.7 lists registers which are "reset to their default values by a power-on reset". Probably, not a "VDD-power-on reset" is meant by this, rather, a backup-domain reset (as defined in chapter 6.1.3). This would be good to clarify, especially when the same "power-on reset" expression is used elsewhere in the RTC chapter, presumably meaning "VDD-power-on-reset" (e.g. in chapter 23.3.5, related to write-protection of the RTC registers) p634 - typo, PREVID_S instead of PREDIV_S p646 - bit SHPF in RTC_ISR is marked as "rc_w0" in the table, however, text indicates that this bit is entirely set and reset by hardware only ("Writing to SHPF has no effect.") thus should be marked as "r". p718 - typo in Fig.244, description of EV6 - "suring" instead of "during" p732 - in I2C_OAR1 and O2C_OAR2, description of ADD[7:1] and ADD2[7:1] fields should read "bits 6:0 of address" rather than "bits 7:1" p777 - the Note saying "You should refer to product specs for availability of the DMA controller [...]" is ridiculous. While appropriate in datasheet of a standalone IP, in a user manual of a particular "product" it should be adjusted for the actual state (as there *is* a DMA controller available for all 6 USART/UART in the ST32F4xx). p798 - in description of Slave select (NSS) pin management, typo in "(SSOE bit in register SPI_CR1)", as SSOE bit is in register SPI_CR2 p834 - in chapter 27.4.7, the text says, "Three status flags are provided..." and then four flags are listed (BSY, TXE, RXNE, CHSIDE) (this is a copy/paste error, as for SPI mode, three status bits are provided, indeed). p837 - it would be nice to see consistent style of "not used in xxx mode" note throughout all SPI/I2S register descriptions (some are in bold, some are italic, while others are normal). p838 - in description of BR[2:0] bits, the separating whitespace between the two columns is missing, causing confused description p839 - in description of bit ERRIE, in the bracket, the text should end by "...in I2S mode" as it was in rev1. Also, regarding the same bracketed text, EERIE enables also FRE in SPI mode, as TI frame format error, according to Table 124 and the text on page 819. p911 - the sentence starting "While MII_RX_EN is deasserted..." probably should read "While MII_RX_DV is deasserted..." - there is no MII_RX_EN signal. p1003 - the reset value of ETH_DMABMR register is incorrectly stated as 0x0000 2101, which would be an invalid value for both PBL and RDP fields. The actual reset value is 0x0002 0101. p1024 - typo on Fig.357 - "duspend" instead of "suspend" p1317 - there is a spurious closing bracket in the paragraph ending "access is complete)." p1355 - typo - "1111: ADDSET phase duration = 1615 x HCLK" apparently ought to be "15 x HCLK" p1355 - typo - "the filed DATLAT" instead of "the field DATLAT" p1415 - typo in "Removed reference *du* Flash programming manual" Random suggestions: - merge and clean up chapters for the timers; the material from timers appnote indicating the difference between timers could be used - mark the SFR bits which are cleared by a *software sequence* (e.g. some of the bits in SPI_SR), in a different way than "true" "read only" bits ---- RM0090 rev 3 p51 - typo " Instructions may also be fetch" instead of "... fetched" p54 - clickable link for SYSCFG section leads to an external document (....\STR_IPs\SYSCFG\Mangusta_SYSCFG.pdf) p56 - in ch.2.3.1, sentence starting "AHB masters support concurrent SRAM accesses..." should probably be as a separate paragraph, outside the "bulleted" list. Also, the bulleted list now lists four blocks of SRAM (as a block has been added for the new 'F42x/F43x). A table would be more appropriate perhaps. Also, the 64kB SRAM is elsewhere referred to as CCM SRAM, why not here. The other two (three) blocks of SRAM could be referred to as SRAM1 to SRAM3, too. I'd rephrase the whole section, making clear that there are two (three) blocks of SRAM accessible through the bus matrix, and one which is not. Also, it's only SRAM1 which could be remapped to the boot area. Also, it may not be as advantageous to remap as it is suggested in this section. p61 - typo in Tab.5, in Size column, for Option bytes 16Kbytes is given (instead of 16 bytes) p63 - In table 7, the maximum clock frequency for 0 waitstate for the lower two voltage ranges are now in discrepancy with corresponding values in the datasheet (datasheet rev.3, table 14). The footnote below table 4 now misses the allowed temperature range for 1.7V operation to be allowed (which is present in the datasheet, as footnote 3 under table 13), is this intentional or by omission? As this table is apparently process-dependent, it should perhaps be moved to datasheet and merged with said table 14 therein. p70 and 71 - tables 11 and 12 it is funny that visual appearance of these two - otherwise indentical tables - is different. With no loss to legibility and little work, these two tables could be merged to one, cutting down the unnecessary fluff. p111 - typo in the chapter title "Reset and clock control for" (the "for" was not there in rev.1 of the manual) p116 - Fig.14, as well as the text under "External source (HSE bypass)" (and also the text under "External source (LSE bypass)" on page 118) indicates that upon bypass the OSC_OUT/OSC32_OUT pin should be "left Hi-Z". This presumably means, that there should be no external circuitry connected to this pin. However, the figure may be (incorrectly?) interpretated also as "the internal circuitry leaves this pin Hi-Z when bypass is set". This should be perhaps clarified. p118 - typo "The LSE crystal is a 32.768 kHz low-speed external (LSE) crystal or ceramic resonator." Should probably read "The LSE clock is [generated from] [...]". The same error is repeated in the beginning of the next section, "The LSE crystal is switched on and off...", should probably read "The LSE clock (or oscillator) is switched on and off..." p175 - Clickable link for "Power control register (PWR_CR)" and "Section 5.1.2 on page 67" lead to an external document (....\STR_IPs\MRCC\PIRANHA_rrcu.pdf"). Referring to "Section 5.1.2 on page 67" for backup domain access is incorrect by page number (backup domain access procedure and usage of DBP bit is described on page 93). p175 - Description of LSEBYP bit says "set and cleared by software to bypass oscillator in debug mode". However, the description of LSE bypass mode on page 118 does not indicate that the bypass mode would require "debug mode". p186 - "Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes." This is confusing. How else could be these registers accessed? p186 - Table 27 for MODER(i)[1:0]=10 (alternate function), the IO configuration column can be interpreted so, that when set to AF, the pin is always output. While there is a remark in 7.3.11 saying "the output buffer is driven by the signal coming from the peripheral (*transmitter enable* and data), which explains, that the peripheral controls whether the pin in AF mode functions as input or output, this should be made clear both in said table, and also in drawings in Figure 17 and Figure 22. p188/189 and elsewhere - in several places, CortexTM-M4F EVENTOUT is referred to; there is no explanation of this feature in ST's nor ARM's publicly available documents. This is unnecessary and confusing. Either a concise explanation should be provided, or else this feature (thus AF15) should be marked as reserved. p198 and on - there is a superfluous slash in (x = A..I/) (also in the form of "C..I/" in the table at the end of chapter) p199 - in description of GPIOx_OTYPER register, the individual bits are marked as OTy[1:0], which is incorrect, as there is only one bit per pin in this register p199 - in description of GPIOx_OSPEEDR register, a mention of the recommended use of compensation cell for speeds above 50MHz, together with link to the related chapter 8.1, should be added Also, the description for highest speed ("11: 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF)") appers to be a mistake (higher speed is expected for lower capacitive load); unfortunately the current version 3 of datasheet provides confusingly non-matching data. p200 - in description of GPIOx_IDR and GPIOx_ODR registers, the individual bits are marked as IDRy[15:0] and ODRy[15:0], which is incorrect, as there is only one bit per pin in this register p205 - in description of SYSCFG_MEMRMP register's reset value, a closing bracket is missing. Also, the description of the MEM_MODE field should contain a link to chapter 2.4. p206 - in description of MII_RMII_SEL bit of SYSCFG_PMC, in the text "RMII Why interface is selected" the word "Why" is probably some spurious relict. p207 - in description of SYSCFG_EXTICR1 register, there is an incorrect index in "0101: PF[C] pin". Also, the reset value is given only as a 16-bit value, which is confusingly different from other registers' description. Also, with little effort, descriptions of all four SYSCFG_EXTICRy (y=1..4) registers could be merged, reducing the unnecessary bloat. p247 - SysTick calibration value according to PM0214: STM32F4xxx Cortex-M4 programming manual, in chapter 4.5.4, should provide 1ms period if HCLK is at maximum, whereas the provided value 18750 is related to a lower than maximum HCLK frequency (150MHz rather than 168MHz). Moreover, while this value is supposed to result in 1ms SysTick interrupt when used as reload value with HCLK=150MHz (and SysTick clocked from HCLK/8) - however, real reload value should be one less than that, so this value in fact results in 1ms reload for HCLK=150.008MHz ... p261 - the description of bits in register EXTI_SWIER says, "Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR." According to both Fig.26 and experiments, this is not entirely true - the corresponding bit in interrupt mask register needs to be set at the moment of write, otherwise the bit in pending register won't be set. Accordingly, the following sentence needs rephrasing, too. Also, while it's true that this register's bit can be cleared by writing 1 into the pending register as the last sentence says, it might be worth noting that it can be cleared by the ordinary writing 0 into it, too. p261 - the desription of bits in register EXTI_PR says, "This bit is cleared by writing a 1 to the bit or by changing the sensitivity of the edge detector." According to experiments, the latter is not true - changing value of corresponding bit in either of the EXTI_RTSR or EXTI_FTSR register did not clear the EXTI_PR bit. p272 - there is insufficient description of what constitutes an external trigger for ADC from TIMx_CHy. The vague description appears to indicate that this is equivalent to the capture event or compare event for the given timer CC channel; from experimentation follows that this is not true at all. It appears, that the ADC trigger is tied to the *output* of the compare circuitry just before it enters the GPIO MUX; from which it is clear, that the timer channel must be configured for compare output, its mode configured so that it actually outputs a waveform (e.g. OCxM cannot be set to FROZEN, CCxE has to be set, etc.), even if it does need to go to actual output pin through the GPIO MUX. A clear description of this issue is needed. Also, it might be a good idea to add a link to this chapter from ther respective Timer chapter (hard to say which one, given the mess the Timer chapters are). p274 - a reference is made to a nonexistent DMA_SxRTR register ("number of transfers configured in the DMA controller’s DMA_SxRTR register"). Probably, the DMA_SxNDTR register is meant by this. Interestingly, in the same subchapter 11.8.1, reference is made to the same register as "adjust destination address and NDTR counter"; again, it would be more appropriate to use the full name of that register (DMA_SxNDTR). p326 - text in chapter 13.4 DCMI Clocks says "The maximum PIXCLK period must be higher than 2.5 HCLK periods." Clearly, the *minimum* PIXCLK period must be higher than 2.5 HCLK periods; in other words, the maximum PIXCLK *frequency* must be less than 0.4 times fHCLK (this is what the datasheet says too, btw.). p387 and p388 - on Figures 116 and 117 (also Fig.186 and Fig.187 on p496), signals such as "cnt_en" are in small letters, whereas everywhere else they are in capital letters p392 - description of MMS bits says "MMS[1:0]" although MMS has 3 bits (the same description for other groups of timers, e.g. on p457 and p499, and p528, simply omits the [x:y] bit size descriptor, as if it would be a single-bit value) p479 - chapter 16.3 apparently ought to be a subchapter in chapter 16.2 (and numbering of other chapters moved accordingly) p479 and p499 and wherever else applicable - according to diagram on Fig.165 and also Tab.77, there is no TRGO output from TIM9 and TIM12, yet chapter 16.5.2 deals with the related MMS bits in TIMx_CR2. p480 and wherever else applicable - conversely to the previous, TIM10, TIM11, TIM13 and TIM14 apparently DO have TRGO output, as according to Tab.77 they serve as masters (for TIM9 and TIM12). However, there is no TIMx_CR2 in the 16.6 subchapter, nor in table 81; and even the reference to it in Figure 166 has been removed (as compared to Rev.1). p512 - some relic "10/11/13/14" just above header of chapter 16.6.2 p627 - chapter 23.3.7 lists registers which are "reset to their default values by a power-on reset". Probably, not a "VDD-power-on reset" is meant by this, rather, a backup-domain reset (as defined in chapter 6.1.3). This would be good to clarify, especially when the same "power-on reset" expression is used elsewhere in the RTC chapter, presumably meaning "VDD-power-on-reset" (e.g. in chapter 23.3.5, related to write-protection of the RTC registers) p629 - typo, PREVID_S instead of PREDIV_S p641 - bit SHPF in RTC_ISR is marked as "rc_w0" in the table, however, text indicates that this bit is entirely set and reset by hardware only ("Writing to SHPF has no effect.") thus should be marked as "r". p714 - typo in Fig.243, description of EV6 - "suring" instead of "during" p773 - the Note saying "You should refer to product specs for availability of the DMA controller [...]" is ridiculous. While appropriate in datasheet of a standalone IP, in a user manual of a particular "product" it should be adjusted for the actual state (as there *is* a DMA controller available for all 6 USART/UART in the ST32F4xx). p830 - in chapter 27.4.7, the text says, "Three status flags are provided..." and then four flags are listed (BSY, TXE, RXNE, CHSIDE) (this is a copy/paste error, as for SPI mode, three status bits are provided, indeed). p794 - in description of Slave select (NSS) pin management, typo in "(SSOE bit in register SPI_CR1)", as SSOE bit is in register SPI_CR2 p833 - there is little reason to mark individual bits of SPI_CR1 as "not used in I2S mode", as it is clearly indicated in the heading of the chapter, that this entire register is not used in I2S mode. Also, it would be nice to see consistent style of this note throughout all register descriptions (some are in bold while others are not). p834 - in description of BR[2:0] bits, the separating whitespace between the two columns is missing, causing confused description p835 - in description of bit ERRIE, in the bracket, the text should end by "...in I2S mode" as it was in rev1. Also, regarding the same bracketed text, EERIE enables also FRE in SPI mode, as TI frame format error, according to Table 122 and the text on page 815. p907 - the sentence starting "While MII_RX_EN is deasserted..." probably should read "While MII_RX_DV is deasserted..." - there is no MII_RX_EN signal. p999 - the reset value of ETH_DMABMR register is incorrectly stated as 0x0000 2101, which would be an invalid value for both PBL and RDP fields. The actual reset value is 0x0002 0101. p1020 - typo on Fig.356 - "duspend" instead of "suspend" p1313 - there is a spurious closing bracket in the paragraph ending "access is complete)." p1348 - typo - "1111: ADDSET phase duration = 1615 x HCLK" apparently ought to be "15 x HCLK" p1348 - typo - "the filed DATLAT" instead of "the field DATLAT" p 1415 - typo in "Removed reference *du* Flash programming manual" Random suggestions: - merge and clean up chapters for the timers; the material from timers appnote indicating the difference between timers could be used - mark the SFR bits which are cleared by a *software sequence* (e.g. some of the bits in SPI_SR), in a different way than "true" "read only" bits ---- RM0090 rev 2 Page number in the footer is set to the other margin compared to rev1, so now when printed as a book, page numbers are printed by the inner margins - is this an intention? p1 - Under "Related documents Available from www.arm.com", documents available from stm.com are listed (not to mention the capitalization error). p48 - typo " Instructions may also be fetch" instead of "... fetched" p50 - in memory map in Table 2, for FSMC control register, there is a bogus line "Section 36.8: FMC register map on page 1592" - there is no section 36, no FMC peripheral and the document ends at page 1340 (that the clickable link leads to an external file, is then well understandable) p51 - clickable link for SYSCFG section leads to an external document (....\STR_IPs\SYSCFG\Mangusta_SYSCFG.pdf) p53 - in ch.2.3.1, sentence starting "AHB masters support concurrent SRAM accesses..." should probably be as a separate paragraph, outside the "bulleted" list. p55 - the sentence "The number of wait states for each voltage range must be extended to acheive [sic] de [sic] maximum frequency at low voltage" is probably an internal remark and should haven't appeared in the manual. In table 4, the maximum clock frequency for 0 waitstate for the lower two voltage ranges are now in discrepancy with corresponding values in the datasheet (datasheet rev.3, table 14). The remark "Prefetch OFF" in the lowest voltage range is confusing and perhpas better be placed as a (more verbose) footnote. The footnote below table 4 now misses the allowed temperature range for 1.7V operation to be allowed, is this intentional or by omission? p89 - typo "The LSE crystal is a 32.768 kHz low-speed external (LSE) crystal or ceramic resonator." Should probably read "The LSE clock is [generated from] [...]". The same error is repeated in the beginning of the next section. p131 - Clickable link for "Power control register (PWR_CR)" and "Section 5.1.2 on page 67" lead to an external document (....\STR_IPs\MRCC\PIRANHA_rrcu.pdf"). Referring to "Section 5.1.2 on page 67" for backup domain access is incorrect both by number of section (should be 4.1.2 - it was correct in rev1) and page number (backup domain access procedure and usage of DBP bit is described on page 66). Description of LSEBYP bit says "set and cleared by software to bypass oscillator in debug mode". However, the description of LSE bypass mode on page 89 does not indicate that the bypass mode would require "debug mode". p151 - in description of GPIOx_OTYPER register, the individual bits are marked as OTy[1:0], which is incorrect, as there is only one bit per pin in this register p153 - in description of GPIOx_IDR and GPIOx_ODR registers, the individual bits are marked as IDRy[15:0] and ODRy[15:0], which is incorrect, as there is only one bit per pin in this register p159 - in description of MII_RMII_SEL bit of SYSCFG_PMC, in the text "RMII Why interface is selected" the word "Why" is probably some spurious relict. p162 - in description of SYSCFG_CMPCR bits, bit 1 is missing (bit 0 is CMP_PD, then bits 2-7 are reserved - apparently it should be bits 1-7) p199 - SysTick calibration value according to PM0214: STM32F4xxx Cortex-M4 programming manual, in chapter 4.5.4, should provide 1ms period if HCLK is at maximum, whereas the provided value 18750 is related to a lower than maximum HCLK frequency (150MHz rather than 168MHz). Moreover, while this value is supposed to result in 1ms SysTick interrupt when used as reload value with HCLK=150MHz (and SysTick clocked from HCLK/8) - however, real reload value should be one less than that, so this value in fact results in 1ms reload for HCLK=150.008MHz ... p209 - the description of bits in register EXTI_SWIER says, "Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR." According to both Fig.26 and experiments, this is not entirely true - the corresponding bit in interrupt mask register needs to be set at the moment of write, otherwise the bit in pending register won't be set. Accordingly, the following sentence needs rephrasing, too. Also, while it's true that this register's bit can be cleared by writing 1 into the pending register as the last sentence says, it might be worth noting that it can be cleared by the ordinary writing 0 into it, too. p209 - the desription of bits in register EXTI_PR says, "This bit is cleared by writing a 1 to the bit or by changing the sensitivity of the edge detector." According to experiments, the latter is not true - changing value of corresponding bit in either of the EXTI_RTSR or EXTI_FTSR register did not clear the EXTI_PR bit. p275 - text in chapter 12.4 DCMI Clocks says "The maximum PIXCLK period must be higher than 2.5 HCLK periods." Clearly, the *minimum* PIXCLK period must be higher than 2.5 HCLK periods; in other words, the maximum PIXCLK *frequency* must be less than 0.4 times fHCLK (this is what the datasheet says too, btw.). p336 and p337 - on Figures 110 and 111, signals such as "cnt_en" are in small letters, whereas everywhere else they are in capital letters p341 - description of MMS bits says "MMS[1:0]" although MMS has 3 bits (the same description for other groups of timers simply omits the [x:y] bit size descriptor, as if it would be a single-bit value) p445 - the same capitalization mismatch in Figures 180 and 181 as in Figures 110 and 111, as described for pages 336-337 above p428 and p450 and p448 and p459 - according to diagram on Fig.159 and also Tab.65, there is no TRGO output from TIM9 and TIM12, yet chapter 15.5.2 and Tab.64 deals with the related MMS bits in TIMx_CR2. p429 and p450 and p469 - conversely to the previous, TIM10, TIM11, TIM13 and TIM14 apparently DO have TRGO output, as according to Tab.65 they serve as masters (for TIM9 and TIM12). However, there is no TIMx_CR2 in the 15.6 subchapter, nor in table 69; and even the reference to it in Figure 160 has been removed (as compared to Rev.1). p461 - some relic "10/11/13/14" just above header of chapter 15.6.2 p538 - clickable link into "Section 5: Reset and clock control (RCC)" leads to an external document (....\STR_IPs\MRCC\SCORPIO_RCC.pdf) p559 - chapter 22.3.7 lists registers reset by "power-on reset". Probably, not a "VDD-power-on reset" is meant by this, rather, a backup-domain reset (as defined in chapter 5.1.3). This would be good to clarify, especially when the same "power-on reset" expression is used elsewhere in the RTC chapter, presumably meaning "VDD-power-on-reset" (e.g. in chapter 22.3.5, related to write-protection of the RTC registers) p561 - typo, PREVID_S instead of PREDIV_S p574 - bit SHPF in RTC_ISR is marked as "rc_w0" in the table, however, text indicates that this bit is entirely set and reset by hardware only thus should be marked as "r". p658 - the Note saying "You should refer to product specs for availability of the DMA controller [...]" is ridiculous. While appropriate in datasheet of a standalone IP, in a user manual of a particular "product" it should be adjusted for the actual state (as there *is* a DMA controller available for all 6 USART/UART in the ST32F4xx). p715 - in chapter 25.4.7, the text says, "Three status flags are provided..." and then four flags are listed (BSY, TXE, RXNE, CHSIDE). p719 - in description of BR[2:0] bits, the separating whitespace between the two columns is missing, causing confused description p720 - in description of bit ERRIE, in the bracket, the text should end by "...in I2S mode" as it was in rev1. Also, regarding the same bracketed text, EERIE enables also FRE in SPI mode, as TI frame format error, according to Table 103 and the text on page 700. In description of FRF bit, the "Note: Not used in I2S mode" lost its "bold" appearance partially, apparently inadvertently... p836 - the sentence starting "While MII_RX_EN is deasserted..." probably should read "While MII_RX_DV is deasserted..." - there is no MII_RX_EN signal. p949 - typo on Fig.350 - "duspend" instead of "suspend" p1276 - typo - "1111: ADDSET phase duration = 1615 x HCLK" apparently ought to be "15 x HCLK" - typo - "the filed DATLAT" instead of "the field DATLAT" ------------------------ RM0090 rev 1 p47 - typo "Height masters:" instead of "Eight masters:" p48 - typo " Instructions may also be fetch" instead of "... fetched" p51 - clickable link for SYSCFG section leads to an external document (....\STR_IPs\SYSCFG\Mangusta_SYSCFG.pdf) p66 - description for access to backup SRAM says in item 3, that SRAM clock is to be enabled through setting BKPSRAMEN bit in the RCC APB1-related register, while BKPSRAMEN is in fact in RCC AHB1 register (the same error is there repated second time in the name of register). p88 - typo "The LSE crystal is a 32.768 kHz low-speed external (LSE) crystal or ceramic resonator." Should probably read "The LSE clock [...]". The same error is repeated in the beginning of the next section. p128 - description of LSEBYP bit says "set and cleared by software to bypass oscillator in debug mode". However, the description of LSE bypass mode on page 89 does not indicate "debug mode", that the bypass mode could not be used normally. p137 and p144 - description of pin set to alternate function both in Table 14 and in the text in chapter 6.3.11 suggests, that a pin set to alternate function is always set as output. This is clearly not the case as the connected peripherals steers the pin's input/output status. Table 14, text in 6.3.11 and Fig.17 should be modified to reflect that. p148 - in description of GPIOx_OTYPER register, the individual bits are marked as OTy[1:0], which is incorrect, as there is only one bit per pin in this register p150 - in description of GPIOx_IDR and GPIOx_ODR registers, the individual bits are marked as IDRy[15:0] and ODRy[15:0], which is incorrect, as there is only one bit per pin in this register p156 - in description of MII_RMII_SEL bit of SYSCFG_PMC, in the text "RMII Why interface is selected" the word "Why" is probably some spurious relict. p159 - in description of SYSCFG_CMPCR bits, bit 1 is missing (bit 0 is CMP_PD, then bits 2-7 are reserved - apparently it should be bits 1-7) p164 - Table 20 - Stream2/Chan2 should read I2S3_EXT_RX - see https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fI2S%20fullduplex%20with%20DMA&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=178 p185 - description of bit 18 in DMA_SxCR register says: "DBM or reserved/rw or r" with no other description why would it be reserved (the respective sub-chapter on double-buffer mode says that double-buffer is available for all streams of both DMAs, so this is probably a copy/paste error from a lower-end device's manual) p195 - in chapter 9.1.2, the description is altogether wrong: the SysTick calibration value [TENMS filed in STK_CALIB read-only register, as described by PM0214: STM32F4xxx Cortex-M4 programming manual, in chapter 4.5.4] reads from the device as 0x493E = 18750 = 150,000/8 supposed to result in 1ms SysTick interrupt when used as reload value with HCLK=150MHz (and SysTick clocked from HCLK/8) - however, real reload value should be one less than that, so this value in fact results in 1ms reload for HCLK=150.008MHz ... p205 - the description of bits in register EXTI_SWIER says, "Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR." According to both Fig.26 and experiments, this is not true - the corresponding bit in interrupt mask register needs to be set at the moment of write, otherwise the bit in pending register won't be set. Accordingly, the following sentence needs rephrasing, too. Also, while it's true that this register's bit can be cleared by writing 1 into the pending register as the last sentence says, it might be worth noting that it can be cleared by the ordinary writing 0 into it, too. p205 - the desription of bits in register EXTI_PR says, "This bit is cleared by writing a 1 to the bit or by changing the sensitivity of the edge detector." According to experiments, the latter is not true - changing value of corresponding bit in either of the EXTI_RTSR or EXTI_FTSR register did not clear the EXTI_PR bit. p270 - text in chapter 12.4 DCMI Clocks says "The maximum PIXCLK period must be higher than 2.5 HCLK periods." Clearly, the *minimum* PIXCLK period must be higher than 2.5 HCLK periods; in other words, the maximum PIXCLK *frequency* must be less than 0.4 times fHCLK (this is what the datasheet says too, btw.). p330 and p331 - on Figures 110 and 111, signals such as "cnt_en" are in small letters, whereas everywhere else they are in capital letters p335 - description of MMS bits says "MMS[1:0]" although MMS has 3 bits (the same description for other groups of timers simply omits the [x:y] bit size descriptor) p373 - the section under Figure 133 ("For example, to configure the upcounter...") is duplicated p394 - description of bit 3 (CCDS) is missing p395 - description of bits 8..15 of TIMx_SMCR register is entirely missing p395 - there is a reference to Table 60, but there is no Table 60 in the manual p432 - the same capitalization mismatch in Figures 174 and 175 as in Figures 110 and 111, as described for pages 330-331 above p435 and p443 - according to diagram on Fig.153 and also Tab.62, there is no TRGO output from TIM9 and TIM12, yet chapter 15.5.2 and Tab.64 deals with the related MSM bits in TIMx_CR2. Conversely, TIM10/TIM11/TIM13/TIM14 have TRGO output yet there is no related TIMx_CR2 register described for them. p539 - typo, PREVID_A instead of PREDIV_A p541 - typo, TC_PRER instead of RTC_PRER p543 - chapter 22.3.7 lists registers reset by "power-on reset". Probably, not a "VDD-power-on reset" is meant by this, rather, a backup-domain reset (as defined in chapter 5.1.3). This would be good to clarify, especially when the same "power-on reset" expression is used elsewhere in the RTC chapter, presumably meaning "VDD-power-on-reset" (e.g. in chapter 22.3.5, related to write-protection of the RTC registers) p544 - typo, PREVID_S instead of PREDIV_S p557 - bit SHPF in RTC_ISR is marked as "rc_w0" in the table, however, text indicates that this bit is entirely set and reset by hardware only thus should be marked as "r". p606-657 - throughout the USART chapter, the total number of pages in the footer is "10" (instead of 1316). p641 - the Note saying "You should refer to product specs for availability of the DMA controller [...]" is ridiculous. While appropriate in datasheet of a standalone IP, in a user manual of a particular "product" it should be adjusted for the actual state (as there *is* a DMA controller available for all 6 USART/UART in the ST32F4xx). p698 - in chapter 25.4.7, the text says, "Three status flags are provided..." and then four flags are listed (BSY, TXE, RXNE, CHSIDE). p810 is missing altogether... (wrong page numbering) p819 - the sentence starting "While MII_RX_EN is deasserted..." probably should read "While MII_RX_DV is deasserted..." - there is no MII_RX_EN signal. p932 - typo on Fig.342 - "duspend" instead of "suspend" p1259 - typo - "1111: ADDSET phase duration = 1615 x HCLK" apparently ought to be "15 x HCLK" p1260 - typo - "the filed DATLAT" instead of "the field DATLAT" multiple - Throughout the whole I2S description, Philips is misspelled as "Phillips" (the same applies to the libraries)