EFTON - STM32 gotchas

32.SPI generates too many clocks in Rx-Only mode, and in Bidirectional mode when turned to Rx

The SPI module in STM32 is relatively complex and features several modes. When set as Master, and set either in Rx-Only mode (SPI_CR1.RXONLY = 1), or in Bidirectional mode turned to Rx (SPI_CR1.BIDIMODE = 1 and SPI_CR1.BIDIOE = 0), it starts to generate clocks on SCK as soon as one of these modes is enabled (and SPI is enabled, SPI_CR1.SPE = 1), and stops generating them only after the given mode is disabled and the current frame is finished.

Naively written code (sometimes seen in "libraries" like Cube) simply turn on these modes and wait until a given number of frames is received, then turn them off. This usually leads to generating more clocks than expected, as the given mode has to be switched off before the last frame is received, more precisely - and I quote here from the RM - between the sampling time of its first bit and before its last bit transfer starts.

This of course means precise timing control, which is not always easily attainable, especially at higher SPI baudrates. Depending on the particular application, techniques like highest-priority timer interrupts or timer-triggered DMA-to-SPI_CR1 transfers might be needed. For receiving a single frame, a simple trick can be used, where the given mode is enabled and then after a few NOP (or NOP-acting) instructions immediately disabled again¹; interrupts need to be disabled for this sequence too.

In many applications, extra clocks don't really matter, but there are slaves where this might be unwanted. Sometimes some framing signal has to be toggled just after transmission, without any extra clocks.

In case of Rx-Only, there's a simple workaround, where the SPI is not used in the Rx-Only mode at all, but using it in "regular" fullduplex mode with the MOSI pin simply not set to any pin in the GPIO AF matrix.

Workaround for Bidirectional mode (i.e. halfduplex, where a single data line is alternated for both directions) is not that simple, and comes at the cost of one extra pin - for this, the SPI would be set to Slave mode, and clocks would be generated on that extra pin, connected externally to SCK, by either a timer/PWM (e.g. using repetition mode, or with two timers in master-slave arrangement, one determining the bitrate on SCK and the other gating it to control the number of pulses); or simply bit-banging the clocks "manually" on pin set as GPIO Out.

1. In Cortex-M7, NOPs may be "gulped" by the pipeline, i.e. they may not contribute to delays. A common workaround is to use DSB. An example of this technique (although without disabling interrupts, probably because there are no interrupts active in that code) can be seen in the example code for reading the LSM303C magnetometer on 32L476GDISCOVERY, which has bidirectional SPI connection.