The '51 is of the harvard architecture (and a rather peculiar variant of it...), so it has separated program and data space. First, we can omit the program space, the program sits there and that is about the all. The program operates on
the internal RAM memory, and Special Function Registers (SFR), which is memory mapped. Particularly, the direct address space of '51 is 256 bytes, with lower 128 bytes (00h-7Fh) occupied by the RAM and the higher 128 bytes (80h-FFh) used as SFR space
. There are less than SFRs, and they are quite "spread" over that space, so there are unused adresses in there (*).
The first confusing thing about the '51 is, that there are no standalone registers as in 8080 and 6800 and their numerous and influential descendants. Rather, one of the SFRs (**) and several RAM locations are used implicitly in many instructions as A (accumulator) and R0 through R7, respectively. When attempting to use these symbols (A and Rx) where direct address is expected (e.g. push A
, mov R1, R2
) the assembler gives an error. Rhe best way is thinking on them as a part of the instruction, e.g. that mov A,xxx
is not a mov
instruction with parameters A and xxx, but a mov A,
instruction with parameter xxx.
To use the accumulator in a direct addressed mode, use its SFR address (E0h) - e.g. push 0E0h
(or better push ACC
- most assemblers have a predefined symbol ACC for E0h). The Rx "registers" are mapped into one of four so called register banks at addresses 00h-07h, 08h-0Fh, 10h-17h, 18h-1Fh, according to the state of RB0 and RB1 flags in the PSW (program status word) register. Therefore, it is not so straighforward to use Rx in direct-mode addressing, it needs to go through an intermediate memory byte or SFR, e.g. mov A,R1
; push ACC
An another addressing mode is the indirect addressing of RAM. Only "registers" R0 and R1 can be used as the address registers, denoted as @R0 and @R1. Note, that the SFR area cannot be accessed by indirect addressing. Instead, the 8052 adds an extra 128 bytes of RAM, with indirect addresses of 80h-FFh.
One peculiarity of the '51 is that many instructions don't use accumulator at all. While accumulator is needed for arithmetics (addition/subtraction and rotations), logic functions (ANL/ORL/XRL for bitwise and, or and exclusive-or) and moves can be performed directly between RAM/SFR and/or constants.
There are also operations performed on bits only (where ofthen the carry bit is involved as a sort of "accumulator") - moves, inversion, and and or even together with inversion of bit, conditional jumps, some with optional simultaneous clearing of the tested bit. The bit addressable area is equal to the RAM addresses 20h-2Fh plus those SFRs which address is x0h or x8h (including ACC, B, PSW and the ports).
Then there are jumps and subroutine calls and returns - the usuall way... save that the SJMP unconditional jump jumps only a signed byte far, AJMP/ACALL jumps/calls within 4kB pages, so there is also a LCALL/LJMP instruction for long jump/call (longer by 1 extra byte). One strange thing is also that there are JZ/JNZ instructions for jump if zero/nonzero, but there is no zero flag in the PSW - the jump is performed depending on current content of accumulator.
Finally, the external data memory can be read and written using MOVX (this involves indirect addressing either via DPTR
or R0/R1). Code memory (either internal or external) can be read only (using DPTR
or the current content of program counter PC, both offset by the current value of accumulator).
- the "bible" - in Intel, Philips and Atmel version
- the final word on 8051
- Michael Karas' opcode chart - illustrative
- 8051ISET the instruction set as a windows helpfile - very useful
(*) In the clones
, this space holds the additional SFRs needed for the added features. The good news is, that the vast majority of manufacturers
obey the unwritten rule to maintain the position and meaning of the original 8051 SFRs. Another unwritten but often kept rule is, that thebits in SFRs which are initialized during reset, are set to zero (except the ports' registers) and their meaning is so that the extra features are by default off. Together with the third unwritten rule of making pin compatible packages if they are DIL40/PLCC44 this means a very good compatibility and easy switching between the clones
- one of the source of '51 platform popularity.
(**) in fact, two, as B is used implicitly in MUL AB and DIV AB instructions. Also, the carry bit is used in bit-move instructions in a similar manner.