When making comparisons to other microcontroller platforms, it is often claimed, that 51's are slow.
This is backed up by the fact, that the traditional 8051 has an instruction cycle executed in 12 oscillator clocks (this is 4 for PIC and 1 for AVR, to mention the most known competitors), and the instructions take up 1 or 2 instruction cycles. Also, the "old" 51's maximum clock was 12MHz, which makes for a "1MIPS" claim (well, very roughly).
Today, the picture is quite different.
While there are still the old-style 12-clockers around, and those make up the "low end - low cost - get it on every corner store" image, most of the manufacturers moved on.
There are two ways how the '51 derivatives
can be made faster - and both are used simultaneously. First, the obvious one, is to increase the clock rate. This is often limited by the speed of the internal program memory (but also by technologycal issues together with cost), so the low-end starts today at 20-24MHz, the middle-range is 33MHz, and some (actually SiLabs
) shoot as high as 100MHz.
The other way is to decrease the number of oscillator cycles per instruction. This is done either in such a style that the number of instruction cycles matches that of the original '51, just there are only 6 (x89x51Rx2) or 2 (P89C51LPC9xx) cycles. Another approach is to match the instruction cycles with the number of program memory fetches (all single-clockers and most of the four-clockers).
Altogether, the sheer performance of modern 8051 derivatives
is typically 10-100 times
higher than of the original 8051; so if the old was 1MIPS, the newer are performing 10-100 MIPS, with still very good mutual compatibility.
See also chips