STM32 gotchas

This is a collection of more or less unexpected or surprising behaviour of STM32 microcontrollers, whether documented or not. What constitutes a gotcha is subjective, and some of the items here are not gotchas at all, just poiting out a feature or idiosyncracy, which may be surprising for some. Also, some of the items are not STM32-specific at all, but apply more broadly to ARM Cortex-M-based mcus, or are related to C or programming generally.

This collection will grow, check back or subscribe to the RSS if you want to follow. Oh yes, no social media, learn how to use real information sources.

Many items are a result of discussion at STM32 forum at community.st.com. I'll try to give relevant links to forum threads where applicable, but they have changed in the past and may do so in the future too, and I won't be able to go and fix all of them.

There's no particular ordering or sorting, it would be hard to find out something half-sane, so just browse through and enjoy.

Legalese: STMicroelectronics registered STM32 as a trademark in various countries, although I don't exactly know what are the ramifications of this, I am not a lawyer. I am not affiliated with ST. In what I write here I may be completely wrong, use below information at your own risk.

Comments are welcome, email them to stm32 at efton dot sk.



  1. Peripheral clock must be enabled in RCC (else registers cannot be written and read as 0)
  2. Timers' clock is 2x APB clock, if APB divider > 1
  3. Advanced timers (TIM1, TIM8, ...), to enable output, need to set TIMx_BDTR.MOE
  4. Debugging is intrusive (e.g. UART/SPI Rx may not work when debugging)
  5. 'F4/'F2 CCM RAM is not good for DMA nor for bit-banding, nor for code
  6. RTC seemingly does not run if only time is read
  7. Interrupt called without reason (late interrupt source clear)
  8. Timer does not work if ARR=0
  9. TIMx->SR &= ~TIM_SR_flag results in lost interrupts (don't RMW or bit-band on status registers)
  10. Strange behaviour after increasing system clock frequency (FLASH latency has to follow system clock)
  11. DAC output does not go rail-to-rail and the output buffer makes it worse
  12. UART parity bit missing as it counts up to data bits
  13. Delay is 1ms longer than required (SW/library, not STM32-specific)
  14. GPIO is not toggling at a rate promised by datasheet
  15. Timer appears to run slower then is set (unrealistically high interrupt rate)
  16. Interrupt does not fire - some troubleshooting hints
  17. Program freezes after enabling an interrupt
  18. ADC readings not as expected because of high signal impedance
  19. Debugger keeps jumping into interrupt when single stepping on 'F746
  20. NDTR problematic when DMA used as Rx FIFO
  21. SPI master NSS unusable
  22. Writing one byte to SPI transmits two bytes (because of data packing)
  23. STM32 hangs in UART interrupt if Rx overrun is not handled
  24. UART Rx stops working (Rx overrun revisited)
  25. STM32 are not microcontrollers, but SoC causing various timing-related issues
  26. Don't use printf() in interrupt or any other lengthy operation
  27. In 'F4, after enabling backup domain access in PWR, wait before accessing RCC_BDCR or BKPSRAM
  28. SPI master does not work as NSS switches it to slave
  29. Processor (and debugger) hangs while debugging OTG USB Host
  30. Only DMA2 can be used to transfer to/from GPIO in 'F4 and 'F2/'F7
  31. Timer - if compare is enabled, setting CCRx > ARR still causes interrupts and DMA and TRGO
  32. SPI generates too many clocks while Rx in Bidir more, and in Rx-only mode
  33. Smaller packages require port remapping for certain functions namely the USB pins PA11 PA12 on 'F042 in TSSOP20
  34. ADC in 'L47x/48x has an extra switch in GPIOx_ASCR
  35. 'F1 don't have the GPIO AF matrix unlike all other STM32 families
  36. Peripherals don't have unique AF number in GPIO matrix they do in 'L1 and mostly do in 'F2/'F4/'F7
  37. GPIO pin input state can still be read, if it's set to Out or AF and EXTI works, too
  38. Analog switch voltage booster (for ADC and other) to be switched on at lower VDD on certain STM32
  39. Software or watchdog reset does not work if NRST is pulled-up hard externally
  40. First TIM period is too short, prescaler does not work - PSC is preloaded; and so is RCR
  41. One TIM period is too long/one PWM pulse is shorter/longer than expected - use preload when needed
  42. First TIM Update ("PeriodElapsed") interrupt fires immediately after configuration when using Cube/SPL
  43. No bit-banding in Cortex-M0/M0+ but not in Cortex-M7 either
  44. Some STM32 models after first programming don't run and need power-on reset (AN2606 pattern6)
  45. Not only frequency but also VOS setting implies FLASH waitstates
  46. Some pins on my Disco/Nucleo/EVAL board don't work as expected
  47. TIMx_CHxN is not inverted if TIMx_CHx is not enabled
  48. TIMx_CHxN cannot be used for input capture
  49. F3 CCM RAM can't be used for DMA but it can be used for code
  50. In 'F4 CRC, data are ignored if written too soon after reset
  51. Not all TIM_CHx are created equal
  52. TIM - in Encoder mode, prescaler must be 0 (otherwise the counted value is nonsense)
  53. TIM does not run if ARR was changed from 0 to nonzero due to ARR preload
  54. In 'F1, RDP also sets write protection on first sectors
  55. 'F2/'F4/'F7/'H7 unreliable at higher frequencies due to incorrect VCAP capacitor
  56. Internal temperature sensor on ADC indicates surprisingly high temperature but it's most probably correct
  57. 'H7 lifetime may be surprisingly short at elevated working temperatures
  58. Changing clock frequency requires careful readjustment of peripherals
  59. PF4 on 'F303 does not work because it's missing on 'F303RD/E
  60. TIM DMA burst (DMAR/DCR) does not work properly if TIMx_DMAR observed in debugger
  61. In 'F42x/43x, erase sector does not work due to confusing sector numbering
  62. Backup domain is not reset by setting RCC_BDCR.BDRST unless PWR_CR.DBP is set, too
  63. Compatibility within the Value Line (0-ending) models
  64. Standard C library function does not work not STM32-specific
  65. Standard C library function (e.g. printf()) fails in interrupt or RTOS not STM32-specific
  66. SPI master Tx outputs 16 clocks, even if its Data Size set to 8 bit keyword: data packing
  67. Where are GPIO AF numbers given for individual pins? And where are the NVIC registers described?
  68. SPI_SR.BSY is unusable
  69. In 'F746/756, ADC triggering from TIM does not work properly but for some cases this can be fixed by switching on DAC
  70. Pins don't work even if set in GPIO due to nonzero default values in 'L0/'L4/'Gx/'H7 GPIOx_MODER
  71. RTC does not work because of RCC_APBxENR.RTCAPBEN bit in some models
  72. No DMA to/from GPIO in 'L0/'G0 i.e. where the Cortex-M0+ core is used
  73. Always read the Errata and not only those directly given for your STM32 model
  74. Write Protection (WRP) granularity may be non-uniform in large-FLASH 'F1/'F0/'F3
  75. Unexpected ETH interrupts after longer uptime due to MAC management counters interrupts being enabled by default
  76. RTC digital calibration does not apply to wakeup period with a specific wakeup source selection
  77. ETH does not work with certain APB2 clock settings due to internal delays between modules
  78. Using TIM input channel filter may produce confusing results if fed with periodic signal
  79. If TIM is set to downcounter, 0% PWM is not possible
  80. When processor stopped in debugger, peripherals and DMA if used by those peripherals keep running
  81. Crash due to stack content getting corrupted DMA writes to buffer improperly allocated on stack
  82. On the RTC readout lock mechanism and its deficiencies
  83. Cannot access BKPSRAM in CubeProgrammer unless register values are manipulated
  84. GPIO pin does not output enough current if set to low GPIO_OSPEEDR setting
  85. Not all GPIO pins are created equal e.g. PA10/PB12 pullup/down in 'F2/'F4/'F7 is only 10kΩ
  86. 'G0/'G4 USB-C Dead Battery conundrum pin influenced by other pin, unexpected pulldowns
  87. UART Tx is not driven immediately after enabling UART and UART_BRR has to be set properly
  88. The Y2k38 bug not STM32-specific
  89. How to set TRGO in TIM16/TIM17? Also, TIM channel needs output enabled if controls another module, e.g. ADC.
  90. Some time after peripheral (TIM, SPI, etc.) function finished, pin state changes resulting in unwanted clock/transition
  91. Some interrupts cannot be disabled, and attempts to do so may lead to HardFault e.g. SysTick
  92. Peripheral connected to other than a single pin in GPIO AF matrix #GPIO_is_poorly_documented
  93. Timers don't support DIR/STEP encoders except in 'G4 - but a trick may exist
  94. 'G4 lifetime may be surprisingly short at elevated working temperatures
  95. How to achieve consistent RTC readout?
  96. TCM don't support highest clock frequencies in 'H723/725
  97. 5V-tolerant pins don't always tolerate 5V especially if mcu is powered down
  98. FLASH is not erased to 0xFF in 'L0 and 'L1 but to 0x00
  99. FLASH is 0xFF but cannot be written if there's ECC and granule has been already written
  100. In lower-end 'F0xx, GPIOC/GPIOD don't have AFR[2] registers
  101. VDDA is pulled high when ADC is enabled if VDDA<2.4V and booster not enabled
  102. STLink-V3 8MHz MCO output is not derived from crystal partial workaround available
  103. After being cleared in NVIC outside an ISR, interrupt reappears if pending flag in NVIC is cleared too soon after removing the interrupt source
  104. USB packet buffer memory in 'F042 is not bytewise writable